\doxysection{stm32h7xx\+\_\+ll\+\_\+spi.\+h}
\hypertarget{stm32h7xx__ll__spi_8h_source}{}\label{stm32h7xx__ll__spi_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_ll\_spi.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_ll\_spi.h}}
\mbox{\hyperlink{stm32h7xx__ll__spi_8h}{Go to the documentation of this file.}}
\begin{DoxyCode}{0}
\DoxyCodeLine{00001\ }
\DoxyCodeLine{00018\ }
\DoxyCodeLine{00019\ \textcolor{comment}{/*\ Define\ to\ prevent\ recursive\ inclusion\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00020\ \textcolor{preprocessor}{\#ifndef\ STM32H7xx\_LL\_SPI\_H}}
\DoxyCodeLine{00021\ \textcolor{preprocessor}{\#define\ STM32H7xx\_LL\_SPI\_H}}
\DoxyCodeLine{00022\ }
\DoxyCodeLine{00023\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{00024\ \textcolor{keyword}{extern}\ \textcolor{stringliteral}{"{}C"{}}\ \{}
\DoxyCodeLine{00025\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00026\ }
\DoxyCodeLine{00027\ \textcolor{comment}{/*\ Includes\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00028\ \textcolor{preprocessor}{\#include\ "{}\mbox{\hyperlink{stm32h7xx_8h}{stm32h7xx.h}}"{}}}
\DoxyCodeLine{00029\ }
\DoxyCodeLine{00033\ }
\DoxyCodeLine{00034\ \textcolor{preprocessor}{\#if\ defined(SPI1)\ ||\ defined(SPI2)\ ||\ defined(SPI3)\ ||\ defined(SPI4)\ ||\ defined(SPI5)\ ||\ defined(SPI6)}}
\DoxyCodeLine{00035\ }
\DoxyCodeLine{00039\ }
\DoxyCodeLine{00040\ \textcolor{comment}{/*\ Private\ variables\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00041\ }
\DoxyCodeLine{00042\ \textcolor{comment}{/*\ Private\ constants\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00043\ }
\DoxyCodeLine{00044\ \textcolor{comment}{/*\ Private\ macros\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00051\ }
\DoxyCodeLine{00052\ \textcolor{comment}{/*\ Exported\ types\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00053\ \textcolor{preprocessor}{\#if\ defined(USE\_FULL\_LL\_DRIVER)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00057\ }
\DoxyCodeLine{00061\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{00062\ \{}
\DoxyCodeLine{00063\ \ \ uint32\_t\ TransferDirection;\ \ \ \ \ \ \ }
\DoxyCodeLine{00068\ }
\DoxyCodeLine{00069\ \ \ uint32\_t\ Mode;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00074\ }
\DoxyCodeLine{00075\ \ \ uint32\_t\ DataWidth;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00080\ }
\DoxyCodeLine{00081\ \ \ uint32\_t\ ClockPolarity;\ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00086\ }
\DoxyCodeLine{00087\ \ \ uint32\_t\ ClockPhase;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00092\ }
\DoxyCodeLine{00093\ \ \ uint32\_t\ NSS;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00100\ }
\DoxyCodeLine{00101\ \ \ uint32\_t\ BaudRate;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00109\ }
\DoxyCodeLine{00110\ \ \ uint32\_t\ BitOrder;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00115\ }
\DoxyCodeLine{00116\ \ \ uint32\_t\ CRCCalculation;\ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00121\ }
\DoxyCodeLine{00122\ \ \ uint32\_t\ CRCPoly;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00128\ }
\DoxyCodeLine{00129\ \}\ LL\_SPI\_InitTypeDef;}
\DoxyCodeLine{00130\ }
\DoxyCodeLine{00134\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*USE\_FULL\_LL\_DRIVER*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{00135\ }
\DoxyCodeLine{00136\ \textcolor{comment}{/*\ Exported\ types\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00137\ }
\DoxyCodeLine{00138\ \textcolor{comment}{/*\ Exported\ constants\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00142\ }
\DoxyCodeLine{00147\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_RXP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_RXP)}}
\DoxyCodeLine{00148\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_TXP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_TXP)}}
\DoxyCodeLine{00149\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_DXP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_DXP)}}
\DoxyCodeLine{00150\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_EOT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_EOT)}}
\DoxyCodeLine{00151\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_TXTF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_TXTF)}}
\DoxyCodeLine{00152\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_UDR\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_UDR)}}
\DoxyCodeLine{00153\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_CRCE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_CRCE)}}
\DoxyCodeLine{00154\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_MODF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_MODF)}}
\DoxyCodeLine{00155\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_OVR\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_OVR)}}
\DoxyCodeLine{00156\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_TIFRE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_TIFRE)}}
\DoxyCodeLine{00157\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_TSERF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_TSERF)}}
\DoxyCodeLine{00158\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_SUSP\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_SUSP)}}
\DoxyCodeLine{00159\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_TXC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_TXC)}}
\DoxyCodeLine{00160\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SR\_RXWNE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_RXWNE)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00164\ }
\DoxyCodeLine{00169\ \textcolor{preprocessor}{\#define\ LL\_SPI\_IER\_RXPIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_IER\_RXPIE)}}
\DoxyCodeLine{00170\ \textcolor{preprocessor}{\#define\ LL\_SPI\_IER\_TXPIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_IER\_TXPIE)}}
\DoxyCodeLine{00171\ \textcolor{preprocessor}{\#define\ LL\_SPI\_IER\_DXPIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_IER\_DXPIE)}}
\DoxyCodeLine{00172\ \textcolor{preprocessor}{\#define\ LL\_SPI\_IER\_EOTIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_IER\_EOTIE)}}
\DoxyCodeLine{00173\ \textcolor{preprocessor}{\#define\ LL\_SPI\_IER\_TXTFIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_IER\_TXTFIE)}}
\DoxyCodeLine{00174\ \textcolor{preprocessor}{\#define\ LL\_SPI\_IER\_UDRIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_IER\_UDRIE)}}
\DoxyCodeLine{00175\ \textcolor{preprocessor}{\#define\ LL\_SPI\_IER\_OVRIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_IER\_OVRIE)}}
\DoxyCodeLine{00176\ \textcolor{preprocessor}{\#define\ LL\_SPI\_IER\_CRCEIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_IER\_CRCEIE)}}
\DoxyCodeLine{00177\ \textcolor{preprocessor}{\#define\ LL\_SPI\_IER\_TIFREIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_IER\_TIFREIE)}}
\DoxyCodeLine{00178\ \textcolor{preprocessor}{\#define\ LL\_SPI\_IER\_MODFIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_IER\_MODFIE)}}
\DoxyCodeLine{00179\ \textcolor{preprocessor}{\#define\ LL\_SPI\_IER\_TSERFIE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_IER\_TSERFIE)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00183\ }
\DoxyCodeLine{00187\ \textcolor{preprocessor}{\#define\ LL\_SPI\_MODE\_MASTER\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MASTER)}}
\DoxyCodeLine{00188\ \textcolor{preprocessor}{\#define\ LL\_SPI\_MODE\_SLAVE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00192\ }
\DoxyCodeLine{00196\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_LEVEL\_HIGH\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CR1\_SSI)}}
\DoxyCodeLine{00197\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_LEVEL\_LOW\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00201\ }
\DoxyCodeLine{00205\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_00CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00206\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_01CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_0)}}
\DoxyCodeLine{00207\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_02CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_1)}}
\DoxyCodeLine{00208\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_03CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_0\ |\ SPI\_CFG2\_MSSI\_1)}}
\DoxyCodeLine{00209\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_04CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_2)}}
\DoxyCodeLine{00210\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_05CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_2\ |\ SPI\_CFG2\_MSSI\_0)}}
\DoxyCodeLine{00211\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_06CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_2\ |\ SPI\_CFG2\_MSSI\_1)}}
\DoxyCodeLine{00212\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_07CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_2\ |\ SPI\_CFG2\_MSSI\_1\ |\ SPI\_CFG2\_MSSI\_0)}}
\DoxyCodeLine{00213\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_08CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_3)}}
\DoxyCodeLine{00214\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_09CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_3\ |\ SPI\_CFG2\_MSSI\_0)}}
\DoxyCodeLine{00215\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_10CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_3\ |\ SPI\_CFG2\_MSSI\_1)}}
\DoxyCodeLine{00216\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_11CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_3\ |\ SPI\_CFG2\_MSSI\_1\ |\ SPI\_CFG2\_MSSI\_0)}}
\DoxyCodeLine{00217\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_12CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_3\ |\ SPI\_CFG2\_MSSI\_2)}}
\DoxyCodeLine{00218\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_13CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_3\ |\ SPI\_CFG2\_MSSI\_2\ |\ SPI\_CFG2\_MSSI\_0)}}
\DoxyCodeLine{00219\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_14CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_3\ |\ SPI\_CFG2\_MSSI\_2\ |\ SPI\_CFG2\_MSSI\_1)}}
\DoxyCodeLine{00220\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SS\_IDLENESS\_15CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MSSI\_3\(\backslash\)}}
\DoxyCodeLine{00221\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG2\_MSSI\_2\ |\ SPI\_CFG2\_MSSI\_1\ |\ SPI\_CFG2\_MSSI\_0)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00225\ }
\DoxyCodeLine{00229\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_00CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00230\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_01CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_0)}}
\DoxyCodeLine{00231\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_02CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_1)}}
\DoxyCodeLine{00232\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_03CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_0\ |\ SPI\_CFG2\_MIDI\_1)}}
\DoxyCodeLine{00233\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_04CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_2)}}
\DoxyCodeLine{00234\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_05CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_2\ |\ SPI\_CFG2\_MIDI\_0)}}
\DoxyCodeLine{00235\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_06CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_2\ |\ SPI\_CFG2\_MIDI\_1)}}
\DoxyCodeLine{00236\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_07CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_2\ |\ SPI\_CFG2\_MIDI\_1\ |\ SPI\_CFG2\_MIDI\_0)}}
\DoxyCodeLine{00237\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_08CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_3)}}
\DoxyCodeLine{00238\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_09CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_3\ |\ SPI\_CFG2\_MIDI\_0)}}
\DoxyCodeLine{00239\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_10CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_3\ |\ SPI\_CFG2\_MIDI\_1)}}
\DoxyCodeLine{00240\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_11CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_3\ |\ SPI\_CFG2\_MIDI\_1\ |\ SPI\_CFG2\_MIDI\_0)}}
\DoxyCodeLine{00241\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_12CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_3\ |\ SPI\_CFG2\_MIDI\_2)}}
\DoxyCodeLine{00242\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_13CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_3\ |\ SPI\_CFG2\_MIDI\_2\ |\ SPI\_CFG2\_MIDI\_0)}}
\DoxyCodeLine{00243\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_14CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_3\ |\ SPI\_CFG2\_MIDI\_2\ |\ SPI\_CFG2\_MIDI\_1)}}
\DoxyCodeLine{00244\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ID\_IDLENESS\_15CYCLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_MIDI\_3\(\backslash\)}}
\DoxyCodeLine{00245\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG2\_MIDI\_2\ |\ SPI\_CFG2\_MIDI\_1\ |\ SPI\_CFG2\_MIDI\_0)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00249\ }
\DoxyCodeLine{00253\ \textcolor{preprocessor}{\#define\ LL\_SPI\_TXCRCINIT\_ALL\_ZERO\_PATTERN\ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00254\ \textcolor{preprocessor}{\#define\ LL\_SPI\_TXCRCINIT\_ALL\_ONES\_PATTERN\ \ \ \ \ \ \ \ \ \ (SPI\_CR1\_TCRCINI)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00258\ }
\DoxyCodeLine{00262\ \textcolor{preprocessor}{\#define\ LL\_SPI\_RXCRCINIT\_ALL\_ZERO\_PATTERN\ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00263\ \textcolor{preprocessor}{\#define\ LL\_SPI\_RXCRCINIT\_ALL\_ONES\_PATTERN\ \ \ \ \ \ \ \ \ \ (SPI\_CR1\_RCRCINI)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00267\ }
\DoxyCodeLine{00271\ \textcolor{preprocessor}{\#define\ LL\_SPI\_UDR\_CONFIG\_REGISTER\_PATTERN\ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00272\ \textcolor{preprocessor}{\#define\ LL\_SPI\_UDR\_CONFIG\_LAST\_RECEIVED\ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_UDRCFG\_0)}}
\DoxyCodeLine{00273\ \textcolor{preprocessor}{\#define\ LL\_SPI\_UDR\_CONFIG\_LAST\_TRANSMITTED\ \ \ \ \ \ \ \ \ (SPI\_CFG1\_UDRCFG\_1)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00277\ }
\DoxyCodeLine{00281\ \textcolor{preprocessor}{\#define\ LL\_SPI\_UDR\_DETECT\_BEGIN\_DATA\_FRAME\ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00282\ \textcolor{preprocessor}{\#define\ LL\_SPI\_UDR\_DETECT\_END\_DATA\_FRAME\ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_UDRDET\_0)}}
\DoxyCodeLine{00283\ \textcolor{preprocessor}{\#define\ LL\_SPI\_UDR\_DETECT\_BEGIN\_ACTIVE\_NSS\ \ \ \ \ \ \ \ \ (SPI\_CFG1\_UDRDET\_1)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00287\ }
\DoxyCodeLine{00291\ \textcolor{preprocessor}{\#define\ LL\_SPI\_PROTOCOL\_MOTOROLA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00292\ \textcolor{preprocessor}{\#define\ LL\_SPI\_PROTOCOL\_TI\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_SP\_0)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00296\ }
\DoxyCodeLine{00300\ \textcolor{preprocessor}{\#define\ LL\_SPI\_PHASE\_1EDGE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00301\ \textcolor{preprocessor}{\#define\ LL\_SPI\_PHASE\_2EDGE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_CPHA)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00305\ }
\DoxyCodeLine{00309\ \textcolor{preprocessor}{\#define\ LL\_SPI\_POLARITY\_LOW\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00310\ \textcolor{preprocessor}{\#define\ LL\_SPI\_POLARITY\_HIGH\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_CPOL)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00314\ }
\DoxyCodeLine{00318\ \textcolor{preprocessor}{\#define\ LL\_SPI\_NSS\_POLARITY\_LOW\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00319\ \textcolor{preprocessor}{\#define\ LL\_SPI\_NSS\_POLARITY\_HIGH\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_SSIOP)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00323\ }
\DoxyCodeLine{00327\ \textcolor{preprocessor}{\#define\ LL\_SPI\_BAUDRATEPRESCALER\_DIV2\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00328\ \textcolor{preprocessor}{\#define\ LL\_SPI\_BAUDRATEPRESCALER\_DIV4\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_MBR\_0)}}
\DoxyCodeLine{00329\ \textcolor{preprocessor}{\#define\ LL\_SPI\_BAUDRATEPRESCALER\_DIV8\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_MBR\_1)}}
\DoxyCodeLine{00330\ \textcolor{preprocessor}{\#define\ LL\_SPI\_BAUDRATEPRESCALER\_DIV16\ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_MBR\_1\ |\ SPI\_CFG1\_MBR\_0)}}
\DoxyCodeLine{00331\ \textcolor{preprocessor}{\#define\ LL\_SPI\_BAUDRATEPRESCALER\_DIV32\ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_MBR\_2)}}
\DoxyCodeLine{00332\ \textcolor{preprocessor}{\#define\ LL\_SPI\_BAUDRATEPRESCALER\_DIV64\ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_MBR\_2\ |\ SPI\_CFG1\_MBR\_0)}}
\DoxyCodeLine{00333\ \textcolor{preprocessor}{\#define\ LL\_SPI\_BAUDRATEPRESCALER\_DIV128\ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_MBR\_2\ |\ SPI\_CFG1\_MBR\_1)}}
\DoxyCodeLine{00334\ \textcolor{preprocessor}{\#define\ LL\_SPI\_BAUDRATEPRESCALER\_DIV256\ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_MBR\_2\ |\ SPI\_CFG1\_MBR\_1\ |\ SPI\_CFG1\_MBR\_0)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00338\ }
\DoxyCodeLine{00342\ \textcolor{preprocessor}{\#define\ LL\_SPI\_LSB\_FIRST\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_LSBFRST)}}
\DoxyCodeLine{00343\ \textcolor{preprocessor}{\#define\ LL\_SPI\_MSB\_FIRST\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00347\ }
\DoxyCodeLine{00351\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FULL\_DUPLEX\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00352\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SIMPLEX\_TX\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_COMM\_0)}}
\DoxyCodeLine{00353\ \textcolor{preprocessor}{\#define\ LL\_SPI\_SIMPLEX\_RX\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_COMM\_1)}}
\DoxyCodeLine{00354\ \textcolor{preprocessor}{\#define\ LL\_SPI\_HALF\_DUPLEX\_RX\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_COMM\_0|SPI\_CFG2\_COMM\_1)}}
\DoxyCodeLine{00355\ \textcolor{preprocessor}{\#define\ LL\_SPI\_HALF\_DUPLEX\_TX\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_COMM\_0|SPI\_CFG2\_COMM\_1|SPI\_CR1\_HDDIR)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00359\ }
\DoxyCodeLine{00363\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_4BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_0\ |\ SPI\_CFG1\_DSIZE\_1)}}
\DoxyCodeLine{00364\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_5BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_2)}}
\DoxyCodeLine{00365\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_6BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_2\ |\ SPI\_CFG1\_DSIZE\_0)}}
\DoxyCodeLine{00366\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_7BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_2\ |\ SPI\_CFG1\_DSIZE\_1)}}
\DoxyCodeLine{00367\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_8BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_2\ |\ SPI\_CFG1\_DSIZE\_1\ |\ SPI\_CFG1\_DSIZE\_0)}}
\DoxyCodeLine{00368\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_9BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_3)}}
\DoxyCodeLine{00369\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_10BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_3\ |\ SPI\_CFG1\_DSIZE\_0)}}
\DoxyCodeLine{00370\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_11BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_3\ |\ SPI\_CFG1\_DSIZE\_1)}}
\DoxyCodeLine{00371\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_12BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_3\ |\ SPI\_CFG1\_DSIZE\_1\ |\ SPI\_CFG1\_DSIZE\_0)}}
\DoxyCodeLine{00372\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_13BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_3\ |\ SPI\_CFG1\_DSIZE\_2)}}
\DoxyCodeLine{00373\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_14BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_3\ |\ SPI\_CFG1\_DSIZE\_2\ |\ SPI\_CFG1\_DSIZE\_0)}}
\DoxyCodeLine{00374\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_15BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_3\ |\ SPI\_CFG1\_DSIZE\_2\ |\ SPI\_CFG1\_DSIZE\_1)}}
\DoxyCodeLine{00375\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_16BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_3\(\backslash\)}}
\DoxyCodeLine{00376\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_DSIZE\_2\ |\ SPI\_CFG1\_DSIZE\_1\ |\ SPI\_CFG1\_DSIZE\_0)}}
\DoxyCodeLine{00377\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_17BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4)}}
\DoxyCodeLine{00378\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_18BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\ |\ SPI\_CFG1\_DSIZE\_0)}}
\DoxyCodeLine{00379\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_19BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\ |\ SPI\_CFG1\_DSIZE\_1)}}
\DoxyCodeLine{00380\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_20BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\ |\ SPI\_CFG1\_DSIZE\_0\ |\ SPI\_CFG1\_DSIZE\_1)}}
\DoxyCodeLine{00381\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_21BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\ |\ SPI\_CFG1\_DSIZE\_2)}}
\DoxyCodeLine{00382\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_22BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\ |\ SPI\_CFG1\_DSIZE\_2\ |\ SPI\_CFG1\_DSIZE\_0)}}
\DoxyCodeLine{00383\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_23BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\ |\ SPI\_CFG1\_DSIZE\_2\ |\ SPI\_CFG1\_DSIZE\_1)}}
\DoxyCodeLine{00384\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_24BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\(\backslash\)}}
\DoxyCodeLine{00385\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_DSIZE\_2\ |\ SPI\_CFG1\_DSIZE\_1\ |\ SPI\_CFG1\_DSIZE\_0)}}
\DoxyCodeLine{00386\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_25BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\ |\ SPI\_CFG1\_DSIZE\_3)}}
\DoxyCodeLine{00387\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_26BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\ |\ SPI\_CFG1\_DSIZE\_3\ |\ SPI\_CFG1\_DSIZE\_0)}}
\DoxyCodeLine{00388\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_27BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\ |\ SPI\_CFG1\_DSIZE\_3\ |\ SPI\_CFG1\_DSIZE\_1)}}
\DoxyCodeLine{00389\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_28BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\(\backslash\)}}
\DoxyCodeLine{00390\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_DSIZE\_3\ |\ SPI\_CFG1\_DSIZE\_1\ |\ SPI\_CFG1\_DSIZE\_0)}}
\DoxyCodeLine{00391\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_29BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\ |\ SPI\_CFG1\_DSIZE\_3\ |\ SPI\_CFG1\_DSIZE\_2)}}
\DoxyCodeLine{00392\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_30BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\(\backslash\)}}
\DoxyCodeLine{00393\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_DSIZE\_3\ |\ SPI\_CFG1\_DSIZE\_2\ |\ SPI\_CFG1\_DSIZE\_0)}}
\DoxyCodeLine{00394\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_31BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\(\backslash\)}}
\DoxyCodeLine{00395\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_DSIZE\_3\ |\ SPI\_CFG1\_DSIZE\_2\ |\ SPI\_CFG1\_DSIZE\_1)}}
\DoxyCodeLine{00396\ \textcolor{preprocessor}{\#define\ LL\_SPI\_DATAWIDTH\_32BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_DSIZE\_4\ |\ SPI\_CFG1\_DSIZE\_3\(\backslash\)}}
\DoxyCodeLine{00397\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_DSIZE\_2\ |\ SPI\_CFG1\_DSIZE\_1\ |\ SPI\_CFG1\_DSIZE\_0)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00401\ }
\DoxyCodeLine{00405\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_01DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00406\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_02DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_0)}}
\DoxyCodeLine{00407\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_03DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_1)}}
\DoxyCodeLine{00408\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_04DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_0\ |\ SPI\_CFG1\_FTHLV\_1)}}
\DoxyCodeLine{00409\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_05DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_2)}}
\DoxyCodeLine{00410\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_06DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_2\ |\ SPI\_CFG1\_FTHLV\_0)}}
\DoxyCodeLine{00411\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_07DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_2\ |\ SPI\_CFG1\_FTHLV\_1)}}
\DoxyCodeLine{00412\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_08DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_2\ |\ SPI\_CFG1\_FTHLV\_1\ |\ SPI\_CFG1\_FTHLV\_0)}}
\DoxyCodeLine{00413\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_09DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_3)}}
\DoxyCodeLine{00414\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_10DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_3\ |\ SPI\_CFG1\_FTHLV\_0)}}
\DoxyCodeLine{00415\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_11DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_3\ |\ SPI\_CFG1\_FTHLV\_1)}}
\DoxyCodeLine{00416\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_12DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_3\ |\ SPI\_CFG1\_FTHLV\_1\ |\ SPI\_CFG1\_FTHLV\_0)}}
\DoxyCodeLine{00417\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_13DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_3\ |\ SPI\_CFG1\_FTHLV\_2)}}
\DoxyCodeLine{00418\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_14DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_3\ |\ SPI\_CFG1\_FTHLV\_2\ |\ SPI\_CFG1\_FTHLV\_0)}}
\DoxyCodeLine{00419\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_15DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_3\ |\ SPI\_CFG1\_FTHLV\_2\ |\ SPI\_CFG1\_FTHLV\_1)}}
\DoxyCodeLine{00420\ \textcolor{preprocessor}{\#define\ LL\_SPI\_FIFO\_TH\_16DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_FTHLV\_3\(\backslash\)}}
\DoxyCodeLine{00421\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_FTHLV\_2\ |\ SPI\_CFG1\_FTHLV\_1\ |\ SPI\_CFG1\_FTHLV\_0)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00425\ }
\DoxyCodeLine{00426\ \textcolor{preprocessor}{\#if\ defined(USE\_FULL\_LL\_DRIVER)}}
\DoxyCodeLine{00427\ }
\DoxyCodeLine{00431\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRCCALCULATION\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00432\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRCCALCULATION\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCEN)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{00436\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ USE\_FULL\_LL\_DRIVER\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00437\ }
\DoxyCodeLine{00441\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_4BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_0\ |\ SPI\_CFG1\_CRCSIZE\_1)}}
\DoxyCodeLine{00442\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_5BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_2)}}
\DoxyCodeLine{00443\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_6BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_2\ |\ SPI\_CFG1\_CRCSIZE\_0)}}
\DoxyCodeLine{00444\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_7BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_2\ |\ SPI\_CFG1\_CRCSIZE\_1)}}
\DoxyCodeLine{00445\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_8BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_2\ |\ SPI\_CFG1\_CRCSIZE\_1\ |\ SPI\_CFG1\_CRCSIZE\_0)}}
\DoxyCodeLine{00446\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_9BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_3)}}
\DoxyCodeLine{00447\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_10BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_3\ |\ SPI\_CFG1\_CRCSIZE\_0)}}
\DoxyCodeLine{00448\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_11BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_3\ |\ SPI\_CFG1\_CRCSIZE\_1)}}
\DoxyCodeLine{00449\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_12BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_3\ |\ SPI\_CFG1\_CRCSIZE\_1\ |\ SPI\_CFG1\_CRCSIZE\_0)}}
\DoxyCodeLine{00450\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_13BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_3\ |\ SPI\_CFG1\_CRCSIZE\_2)}}
\DoxyCodeLine{00451\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_14BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_3\ |\ SPI\_CFG1\_CRCSIZE\_2\ |\ SPI\_CFG1\_CRCSIZE\_0)}}
\DoxyCodeLine{00452\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_15BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_3\ |\ SPI\_CFG1\_CRCSIZE\_2\ |\ SPI\_CFG1\_CRCSIZE\_1)}}
\DoxyCodeLine{00453\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_16BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_3\(\backslash\)}}
\DoxyCodeLine{00454\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_CRCSIZE\_2\ |\ SPI\_CFG1\_CRCSIZE\_1\ |\ SPI\_CFG1\_CRCSIZE\_0)}}
\DoxyCodeLine{00455\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_17BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4)}}
\DoxyCodeLine{00456\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_18BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\ |\ SPI\_CFG1\_CRCSIZE\_0)}}
\DoxyCodeLine{00457\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_19BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\ |\ SPI\_CFG1\_CRCSIZE\_1)}}
\DoxyCodeLine{00458\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_20BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\ |\ SPI\_CFG1\_CRCSIZE\_0\ |\ SPI\_CFG1\_CRCSIZE\_1)}}
\DoxyCodeLine{00459\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_21BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\ |\ SPI\_CFG1\_CRCSIZE\_2)}}
\DoxyCodeLine{00460\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_22BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\ |\ SPI\_CFG1\_CRCSIZE\_2\ |\ SPI\_CFG1\_CRCSIZE\_0)}}
\DoxyCodeLine{00461\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_23BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\ |\ SPI\_CFG1\_CRCSIZE\_2\ |\ SPI\_CFG1\_CRCSIZE\_1)}}
\DoxyCodeLine{00462\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_24BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\(\backslash\)}}
\DoxyCodeLine{00463\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_CRCSIZE\_2\ |\ SPI\_CFG1\_CRCSIZE\_1\ |\ SPI\_CFG1\_CRCSIZE\_0)}}
\DoxyCodeLine{00464\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_25BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\ |\ SPI\_CFG1\_CRCSIZE\_3)}}
\DoxyCodeLine{00465\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_26BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\ |\ SPI\_CFG1\_CRCSIZE\_3\ |\ SPI\_CFG1\_CRCSIZE\_0)}}
\DoxyCodeLine{00466\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_27BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\ |\ SPI\_CFG1\_CRCSIZE\_3\ |\ SPI\_CFG1\_CRCSIZE\_1)}}
\DoxyCodeLine{00467\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_28BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\(\backslash\)}}
\DoxyCodeLine{00468\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_CRCSIZE\_3\ |\ SPI\_CFG1\_CRCSIZE\_1\ |\ SPI\_CFG1\_CRCSIZE\_0)}}
\DoxyCodeLine{00469\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_29BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\ |\ SPI\_CFG1\_CRCSIZE\_3\ |\ SPI\_CFG1\_CRCSIZE\_2)}}
\DoxyCodeLine{00470\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_30BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\(\backslash\)}}
\DoxyCodeLine{00471\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_CRCSIZE\_3\ |\ SPI\_CFG1\_CRCSIZE\_2\ |\ SPI\_CFG1\_CRCSIZE\_0)}}
\DoxyCodeLine{00472\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_31BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\(\backslash\)}}
\DoxyCodeLine{00473\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_CRCSIZE\_3\ |\ SPI\_CFG1\_CRCSIZE\_2\ |\ SPI\_CFG1\_CRCSIZE\_1)}}
\DoxyCodeLine{00474\ \textcolor{preprocessor}{\#define\ LL\_SPI\_CRC\_32BIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG1\_CRCSIZE\_4\ |\ SPI\_CFG1\_CRCSIZE\_3\(\backslash\)}}
\DoxyCodeLine{00475\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ SPI\_CFG1\_CRCSIZE\_2\ |\ SPI\_CFG1\_CRCSIZE\_1\ |\ SPI\_CFG1\_CRCSIZE\_0)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00479\ }
\DoxyCodeLine{00483\ \textcolor{preprocessor}{\#define\ LL\_SPI\_NSS\_SOFT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_SSM)}}
\DoxyCodeLine{00484\ \textcolor{preprocessor}{\#define\ LL\_SPI\_NSS\_HARD\_INPUT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{00485\ \textcolor{preprocessor}{\#define\ LL\_SPI\_NSS\_HARD\_OUTPUT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_CFG2\_SSOE)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00489\ }
\DoxyCodeLine{00493\ \textcolor{preprocessor}{\#define\ LL\_SPI\_RX\_FIFO\_0PACKET\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)\ \ \ \ }\textcolor{comment}{/*\ 0\ or\ multiple\ of\ 4\ packet\ available\ is\ the\ RxFIFO\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00494\ \textcolor{preprocessor}{\#define\ LL\_SPI\_RX\_FIFO\_1PACKET\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_RXPLVL\_0)}}
\DoxyCodeLine{00495\ \textcolor{preprocessor}{\#define\ LL\_SPI\_RX\_FIFO\_2PACKET\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_RXPLVL\_1)}}
\DoxyCodeLine{00496\ \textcolor{preprocessor}{\#define\ LL\_SPI\_RX\_FIFO\_3PACKET\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_SR\_RXPLVL\_1\ |\ SPI\_SR\_RXPLVL\_0)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00500\ }
\DoxyCodeLine{00504\ }
\DoxyCodeLine{00505\ \textcolor{comment}{/*\ Exported\ macro\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00509\ }
\DoxyCodeLine{00513\ }
\DoxyCodeLine{00521\ \textcolor{preprocessor}{\#define\ LL\_SPI\_WriteReg(\_\_INSTANCE\_\_,\ \_\_REG\_\_,\ \_\_VALUE\_\_)\ WRITE\_REG(\_\_INSTANCE\_\_-\/>\_\_REG\_\_,\ (\_\_VALUE\_\_))}}
\DoxyCodeLine{00522\ }
\DoxyCodeLine{00529\ \textcolor{preprocessor}{\#define\ LL\_SPI\_ReadReg(\_\_INSTANCE\_\_,\ \_\_REG\_\_)\ READ\_REG(\_\_INSTANCE\_\_-\/>\_\_REG\_\_)}\textcolor{preprocessor}{}}
\DoxyCodeLine{00533\ }
\DoxyCodeLine{00537\ }
\DoxyCodeLine{00538\ }
\DoxyCodeLine{00539\ \textcolor{comment}{/*\ Exported\ functions\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00540\ }
\DoxyCodeLine{00544\ }
\DoxyCodeLine{00548\ }
\DoxyCodeLine{00555\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_Enable(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00556\ \{}
\DoxyCodeLine{00557\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac5a646d978d3b98eb7c6a5d95d75c3f9}{SPI\_CR1\_SPE}});}
\DoxyCodeLine{00558\ \}}
\DoxyCodeLine{00559\ }
\DoxyCodeLine{00567\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_Disable(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00568\ \{}
\DoxyCodeLine{00569\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac5a646d978d3b98eb7c6a5d95d75c3f9}{SPI\_CR1\_SPE}});}
\DoxyCodeLine{00570\ \}}
\DoxyCodeLine{00571\ }
\DoxyCodeLine{00578\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabled(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00579\ \{}
\DoxyCodeLine{00580\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac5a646d978d3b98eb7c6a5d95d75c3f9}{SPI\_CR1\_SPE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac5a646d978d3b98eb7c6a5d95d75c3f9}{SPI\_CR1\_SPE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{00581\ \}}
\DoxyCodeLine{00582\ }
\DoxyCodeLine{00590\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIOSwap(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00591\ \{}
\DoxyCodeLine{00592\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6a392a021319a1e0fdf422502cfa47f2}{SPI\_CFG2\_IOSWP}});}
\DoxyCodeLine{00593\ \}}
\DoxyCodeLine{00594\ }
\DoxyCodeLine{00602\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableIOSwap(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00603\ \{}
\DoxyCodeLine{00604\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6a392a021319a1e0fdf422502cfa47f2}{SPI\_CFG2\_IOSWP}});}
\DoxyCodeLine{00605\ \}}
\DoxyCodeLine{00606\ }
\DoxyCodeLine{00613\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIOSwap(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00614\ \{}
\DoxyCodeLine{00615\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6a392a021319a1e0fdf422502cfa47f2}{SPI\_CFG2\_IOSWP}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6a392a021319a1e0fdf422502cfa47f2}{SPI\_CFG2\_IOSWP}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{00616\ \}}
\DoxyCodeLine{00617\ }
\DoxyCodeLine{00625\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableGPIOControl(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00626\ \{}
\DoxyCodeLine{00627\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf0d90225cbbced8ab5c382605500e6b8}{SPI\_CFG2\_AFCNTR}});}
\DoxyCodeLine{00628\ \}}
\DoxyCodeLine{00629\ }
\DoxyCodeLine{00637\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableGPIOControl(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00638\ \{}
\DoxyCodeLine{00639\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf0d90225cbbced8ab5c382605500e6b8}{SPI\_CFG2\_AFCNTR}});}
\DoxyCodeLine{00640\ \}}
\DoxyCodeLine{00641\ }
\DoxyCodeLine{00648\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledGPIOControl(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00649\ \{}
\DoxyCodeLine{00650\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf0d90225cbbced8ab5c382605500e6b8}{SPI\_CFG2\_AFCNTR}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf0d90225cbbced8ab5c382605500e6b8}{SPI\_CFG2\_AFCNTR}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{00651\ \}}
\DoxyCodeLine{00652\ }
\DoxyCodeLine{00663\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetMode(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ Mode)}
\DoxyCodeLine{00664\ \{}
\DoxyCodeLine{00665\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae374f7d95b2b790e5741a84932b8c63f}{SPI\_CFG2\_MASTER}},\ Mode);}
\DoxyCodeLine{00666\ \}}
\DoxyCodeLine{00667\ }
\DoxyCodeLine{00676\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00677\ \{}
\DoxyCodeLine{00678\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae374f7d95b2b790e5741a84932b8c63f}{SPI\_CFG2\_MASTER}}));}
\DoxyCodeLine{00679\ \}}
\DoxyCodeLine{00680\ }
\DoxyCodeLine{00704\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetMasterSSIdleness(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ MasterSSIdleness)}
\DoxyCodeLine{00705\ \{}
\DoxyCodeLine{00706\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga83164e8c254119b5b02b761d666ef12c}{SPI\_CFG2\_MSSI}},\ MasterSSIdleness);}
\DoxyCodeLine{00707\ \}}
\DoxyCodeLine{00708\ }
\DoxyCodeLine{00731\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetMasterSSIdleness(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00732\ \{}
\DoxyCodeLine{00733\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga83164e8c254119b5b02b761d666ef12c}{SPI\_CFG2\_MSSI}}));}
\DoxyCodeLine{00734\ \}}
\DoxyCodeLine{00735\ }
\DoxyCodeLine{00759\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetInterDataIdleness(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ MasterInterDataIdleness)}
\DoxyCodeLine{00760\ \{}
\DoxyCodeLine{00761\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab902d7b8309b8fedfd9b338618774191}{SPI\_CFG2\_MIDI}},\ MasterInterDataIdleness);}
\DoxyCodeLine{00762\ \}}
\DoxyCodeLine{00763\ }
\DoxyCodeLine{00786\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetInterDataIdleness(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00787\ \{}
\DoxyCodeLine{00788\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab902d7b8309b8fedfd9b338618774191}{SPI\_CFG2\_MIDI}}));}
\DoxyCodeLine{00789\ \}}
\DoxyCodeLine{00790\ }
\DoxyCodeLine{00799\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetTransferSize(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ Count)}
\DoxyCodeLine{00800\ \{}
\DoxyCodeLine{00801\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a38cb89a872e456e6ecd29b6c71d85600}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf679040af74b6aefa72766069dc7b0f8}{SPI\_CR2\_TSIZE}},\ Count);}
\DoxyCodeLine{00802\ \}}
\DoxyCodeLine{00803\ }
\DoxyCodeLine{00811\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetTransferSize(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00812\ \{}
\DoxyCodeLine{00813\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a38cb89a872e456e6ecd29b6c71d85600}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf679040af74b6aefa72766069dc7b0f8}{SPI\_CR2\_TSIZE}}));}
\DoxyCodeLine{00814\ \}}
\DoxyCodeLine{00815\ }
\DoxyCodeLine{00824\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetReloadSize(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ Count)}
\DoxyCodeLine{00825\ \{}
\DoxyCodeLine{00826\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a38cb89a872e456e6ecd29b6c71d85600}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga68f0df5875b67a12e55d99ff0da2d38b}{SPI\_CR2\_TSER}},\ Count\ <<\ SPI\_CR2\_TSER\_Pos);}
\DoxyCodeLine{00827\ \}}
\DoxyCodeLine{00828\ }
\DoxyCodeLine{00836\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetReloadSize(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00837\ \{}
\DoxyCodeLine{00838\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a38cb89a872e456e6ecd29b6c71d85600}{CR2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga68f0df5875b67a12e55d99ff0da2d38b}{SPI\_CR2\_TSER}})\ >>\ SPI\_CR2\_TSER\_Pos);}
\DoxyCodeLine{00839\ \}}
\DoxyCodeLine{00840\ }
\DoxyCodeLine{00849\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIOLock(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00850\ \{}
\DoxyCodeLine{00851\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga924de6adac104ed55c282c0d061ac11f}{SPI\_CR1\_IOLOCK}});}
\DoxyCodeLine{00852\ \}}
\DoxyCodeLine{00853\ }
\DoxyCodeLine{00860\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIOLock(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00861\ \{}
\DoxyCodeLine{00862\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga924de6adac104ed55c282c0d061ac11f}{SPI\_CR1\_IOLOCK}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga924de6adac104ed55c282c0d061ac11f}{SPI\_CR1\_IOLOCK}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{00863\ \}}
\DoxyCodeLine{00864\ }
\DoxyCodeLine{00874\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetTxCRCInitPattern(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ TXCRCInitAll)}
\DoxyCodeLine{00875\ \{}
\DoxyCodeLine{00876\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaad0484985babc3a9f84957458281337c}{SPI\_CR1\_TCRCINI}},\ TXCRCInitAll);}
\DoxyCodeLine{00877\ \}}
\DoxyCodeLine{00878\ }
\DoxyCodeLine{00887\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetTxCRCInitPattern(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00888\ \{}
\DoxyCodeLine{00889\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaad0484985babc3a9f84957458281337c}{SPI\_CR1\_TCRCINI}}));}
\DoxyCodeLine{00890\ \}}
\DoxyCodeLine{00891\ }
\DoxyCodeLine{00901\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetRxCRCInitPattern(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ RXCRCInitAll)}
\DoxyCodeLine{00902\ \{}
\DoxyCodeLine{00903\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaacb99dd866a50efb470836aed787f273}{SPI\_CR1\_RCRCINI}},\ RXCRCInitAll);}
\DoxyCodeLine{00904\ \}}
\DoxyCodeLine{00905\ }
\DoxyCodeLine{00914\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetRxCRCInitPattern(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00915\ \{}
\DoxyCodeLine{00916\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaacb99dd866a50efb470836aed787f273}{SPI\_CR1\_RCRCINI}}));}
\DoxyCodeLine{00917\ \}}
\DoxyCodeLine{00918\ }
\DoxyCodeLine{00929\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetInternalSSLevel(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ SSLevel)}
\DoxyCodeLine{00930\ \{}
\DoxyCodeLine{00931\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5f154374b58c0234f82ea326cb303a1e}{SPI\_CR1\_SSI}},\ SSLevel);}
\DoxyCodeLine{00932\ \}}
\DoxyCodeLine{00933\ }
\DoxyCodeLine{00942\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetInternalSSLevel(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00943\ \{}
\DoxyCodeLine{00944\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5f154374b58c0234f82ea326cb303a1e}{SPI\_CR1\_SSI}}));}
\DoxyCodeLine{00945\ \}}
\DoxyCodeLine{00946\ }
\DoxyCodeLine{00953\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableFullSizeCRC(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00954\ \{}
\DoxyCodeLine{00955\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaa106cc55ef294cde0f750aebd117aad}{SPI\_CR1\_CRC33\_17}});}
\DoxyCodeLine{00956\ \}}
\DoxyCodeLine{00957\ }
\DoxyCodeLine{00964\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableFullSizeCRC(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00965\ \{}
\DoxyCodeLine{00966\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaa106cc55ef294cde0f750aebd117aad}{SPI\_CR1\_CRC33\_17}});}
\DoxyCodeLine{00967\ \}}
\DoxyCodeLine{00968\ }
\DoxyCodeLine{00975\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledFullSizeCRC(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00976\ \{}
\DoxyCodeLine{00977\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaa106cc55ef294cde0f750aebd117aad}{SPI\_CR1\_CRC33\_17}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaa106cc55ef294cde0f750aebd117aad}{SPI\_CR1\_CRC33\_17}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{00978\ \}}
\DoxyCodeLine{00979\ }
\DoxyCodeLine{00986\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SuspendMasterTransfer(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00987\ \{}
\DoxyCodeLine{00988\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac11913f93aaad350abb857fccf2654c2}{SPI\_CR1\_CSUSP}});}
\DoxyCodeLine{00989\ \}}
\DoxyCodeLine{00990\ }
\DoxyCodeLine{00997\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_StartMasterTransfer(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{00998\ \{}
\DoxyCodeLine{00999\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1304286c75b4eea9246faa8aea8d9d35}{SPI\_CR1\_CSTART}});}
\DoxyCodeLine{01000\ \}}
\DoxyCodeLine{01001\ }
\DoxyCodeLine{01008\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveMasterTransfer(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01009\ \{}
\DoxyCodeLine{01010\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1304286c75b4eea9246faa8aea8d9d35}{SPI\_CR1\_CSTART}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1304286c75b4eea9246faa8aea8d9d35}{SPI\_CR1\_CSTART}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01011\ \}}
\DoxyCodeLine{01012\ }
\DoxyCodeLine{01019\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableMasterRxAutoSuspend(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01020\ \{}
\DoxyCodeLine{01021\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae7d399759fc0606d8ef44845004a9faf}{SPI\_CR1\_MASRX}});}
\DoxyCodeLine{01022\ \}}
\DoxyCodeLine{01023\ }
\DoxyCodeLine{01030\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableMasterRxAutoSuspend(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01031\ \{}
\DoxyCodeLine{01032\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae7d399759fc0606d8ef44845004a9faf}{SPI\_CR1\_MASRX}});}
\DoxyCodeLine{01033\ \}}
\DoxyCodeLine{01034\ }
\DoxyCodeLine{01041\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledMasterRxAutoSuspend(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01042\ \{}
\DoxyCodeLine{01043\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae7d399759fc0606d8ef44845004a9faf}{SPI\_CR1\_MASRX}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae7d399759fc0606d8ef44845004a9faf}{SPI\_CR1\_MASRX}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01044\ \}}
\DoxyCodeLine{01045\ }
\DoxyCodeLine{01057\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetUDRConfiguration(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ UDRConfig)}
\DoxyCodeLine{01058\ \{}
\DoxyCodeLine{01059\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gafbc576a4e016b13218347fd2bd3303db}{SPI\_CFG1\_UDRCFG}},\ UDRConfig);}
\DoxyCodeLine{01060\ \}}
\DoxyCodeLine{01061\ }
\DoxyCodeLine{01071\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetUDRConfiguration(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01072\ \{}
\DoxyCodeLine{01073\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gafbc576a4e016b13218347fd2bd3303db}{SPI\_CFG1\_UDRCFG}}));}
\DoxyCodeLine{01074\ \}}
\DoxyCodeLine{01075\ }
\DoxyCodeLine{01087\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetUDRDetection(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ UDRDetection)}
\DoxyCodeLine{01088\ \{}
\DoxyCodeLine{01089\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gabcf5fdb75a84ac9a9634205b1dcbff3d}{SPI\_CFG1\_UDRDET}},\ UDRDetection);}
\DoxyCodeLine{01090\ \}}
\DoxyCodeLine{01091\ }
\DoxyCodeLine{01101\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetUDRDetection(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01102\ \{}
\DoxyCodeLine{01103\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gabcf5fdb75a84ac9a9634205b1dcbff3d}{SPI\_CFG1\_UDRDET}}));}
\DoxyCodeLine{01104\ \}}
\DoxyCodeLine{01105\ }
\DoxyCodeLine{01116\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetStandard(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ Standard)}
\DoxyCodeLine{01117\ \{}
\DoxyCodeLine{01118\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga63c870e907f27d909d0eaff45f4ce20d}{SPI\_CFG2\_SP}},\ Standard);}
\DoxyCodeLine{01119\ \}}
\DoxyCodeLine{01120\ }
\DoxyCodeLine{01129\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetStandard(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01130\ \{}
\DoxyCodeLine{01131\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga63c870e907f27d909d0eaff45f4ce20d}{SPI\_CFG2\_SP}}));}
\DoxyCodeLine{01132\ \}}
\DoxyCodeLine{01133\ }
\DoxyCodeLine{01145\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetClockPhase(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ ClockPhase)}
\DoxyCodeLine{01146\ \{}
\DoxyCodeLine{01147\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga268bfe1b80b116394eef88b75cd3bcbd}{SPI\_CFG2\_CPHA}},\ ClockPhase);}
\DoxyCodeLine{01148\ \}}
\DoxyCodeLine{01149\ }
\DoxyCodeLine{01158\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetClockPhase(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01159\ \{}
\DoxyCodeLine{01160\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga268bfe1b80b116394eef88b75cd3bcbd}{SPI\_CFG2\_CPHA}}));}
\DoxyCodeLine{01161\ \}}
\DoxyCodeLine{01162\ }
\DoxyCodeLine{01174\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetClockPolarity(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ ClockPolarity)}
\DoxyCodeLine{01175\ \{}
\DoxyCodeLine{01176\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf9e5874b94f69e2af8d7fd460ff33460}{SPI\_CFG2\_CPOL}},\ ClockPolarity);}
\DoxyCodeLine{01177\ \}}
\DoxyCodeLine{01178\ }
\DoxyCodeLine{01187\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetClockPolarity(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01188\ \{}
\DoxyCodeLine{01189\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf9e5874b94f69e2af8d7fd460ff33460}{SPI\_CFG2\_CPOL}}));}
\DoxyCodeLine{01190\ \}}
\DoxyCodeLine{01191\ }
\DoxyCodeLine{01203\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetNSSPolarity(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ NSSPolarity)}
\DoxyCodeLine{01204\ \{}
\DoxyCodeLine{01205\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa1829b079924734042d20b1671fecc1d}{SPI\_CFG2\_SSIOP}},\ NSSPolarity);}
\DoxyCodeLine{01206\ \}}
\DoxyCodeLine{01207\ }
\DoxyCodeLine{01216\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetNSSPolarity(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01217\ \{}
\DoxyCodeLine{01218\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa1829b079924734042d20b1671fecc1d}{SPI\_CFG2\_SSIOP}}));}
\DoxyCodeLine{01219\ \}}
\DoxyCodeLine{01220\ }
\DoxyCodeLine{01238\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetBaudRatePrescaler(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ Baudrate)}
\DoxyCodeLine{01239\ \{}
\DoxyCodeLine{01240\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4a94302de465966446b502162851b455}{SPI\_CFG1\_MBR}},\ Baudrate);}
\DoxyCodeLine{01241\ \}}
\DoxyCodeLine{01242\ }
\DoxyCodeLine{01257\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetBaudRatePrescaler(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01258\ \{}
\DoxyCodeLine{01259\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4a94302de465966446b502162851b455}{SPI\_CFG1\_MBR}}));}
\DoxyCodeLine{01260\ \}}
\DoxyCodeLine{01261\ }
\DoxyCodeLine{01273\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetTransferBitOrder(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ BitOrder)}
\DoxyCodeLine{01274\ \{}
\DoxyCodeLine{01275\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaff6b7fae6de0289fd47beb27c3120b9}{SPI\_CFG2\_LSBFRST}},\ BitOrder);}
\DoxyCodeLine{01276\ \}}
\DoxyCodeLine{01277\ }
\DoxyCodeLine{01286\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetTransferBitOrder(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01287\ \{}
\DoxyCodeLine{01288\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaaff6b7fae6de0289fd47beb27c3120b9}{SPI\_CFG2\_LSBFRST}}));}
\DoxyCodeLine{01289\ \}}
\DoxyCodeLine{01290\ }
\DoxyCodeLine{01306\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetTransferDirection(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ TransferDirection)}
\DoxyCodeLine{01307\ \{}
\DoxyCodeLine{01308\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga71105846351660951df077c563a0a437}{SPI\_CR1\_HDDIR}},\ \ TransferDirection\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga71105846351660951df077c563a0a437}{SPI\_CR1\_HDDIR}});}
\DoxyCodeLine{01309\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1b7bf18425d7ade65a2e772fde619bf1}{SPI\_CFG2\_COMM}},\ TransferDirection\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1b7bf18425d7ade65a2e772fde619bf1}{SPI\_CFG2\_COMM}});}
\DoxyCodeLine{01310\ \}}
\DoxyCodeLine{01311\ }
\DoxyCodeLine{01324\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetTransferDirection(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01325\ \{}
\DoxyCodeLine{01326\ \ \ uint32\_t\ Hddir\ =\ READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga71105846351660951df077c563a0a437}{SPI\_CR1\_HDDIR}});}
\DoxyCodeLine{01327\ \ \ uint32\_t\ Comm\ =\ READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1b7bf18425d7ade65a2e772fde619bf1}{SPI\_CFG2\_COMM}});}
\DoxyCodeLine{01328\ \ \ \textcolor{keywordflow}{return}\ (Hddir\ |\ Comm);}
\DoxyCodeLine{01329\ \}}
\DoxyCodeLine{01330\ }
\DoxyCodeLine{01341\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetHalfDuplexDirection(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ HalfDuplexDirection)}
\DoxyCodeLine{01342\ \{}
\DoxyCodeLine{01343\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga71105846351660951df077c563a0a437}{SPI\_CR1\_HDDIR}},\ HalfDuplexDirection\ \&\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga71105846351660951df077c563a0a437}{SPI\_CR1\_HDDIR}});}
\DoxyCodeLine{01344\ \}}
\DoxyCodeLine{01345\ }
\DoxyCodeLine{01355\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetHalfDuplexDirection(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01356\ \{}
\DoxyCodeLine{01357\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga71105846351660951df077c563a0a437}{SPI\_CR1\_HDDIR}})\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1b7bf18425d7ade65a2e772fde619bf1}{SPI\_CFG2\_COMM}});}
\DoxyCodeLine{01358\ \}}
\DoxyCodeLine{01359\ }
\DoxyCodeLine{01397\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetDataWidth(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ DataWidth)}
\DoxyCodeLine{01398\ \{}
\DoxyCodeLine{01399\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab9090ae865e0d132177fb39e812faa21}{SPI\_CFG1\_DSIZE}},\ DataWidth);}
\DoxyCodeLine{01400\ \}}
\DoxyCodeLine{01401\ }
\DoxyCodeLine{01437\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetDataWidth(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01438\ \{}
\DoxyCodeLine{01439\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab9090ae865e0d132177fb39e812faa21}{SPI\_CFG1\_DSIZE}}));}
\DoxyCodeLine{01440\ \}}
\DoxyCodeLine{01441\ }
\DoxyCodeLine{01466\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetFIFOThreshold(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ Threshold)}
\DoxyCodeLine{01467\ \{}
\DoxyCodeLine{01468\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5a1c7f82a6ed86099d121c4d6dfc63a9}{SPI\_CFG1\_FTHLV}},\ Threshold);}
\DoxyCodeLine{01469\ \}}
\DoxyCodeLine{01470\ }
\DoxyCodeLine{01493\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetFIFOThreshold(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01494\ \{}
\DoxyCodeLine{01495\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5a1c7f82a6ed86099d121c4d6dfc63a9}{SPI\_CFG1\_FTHLV}}));}
\DoxyCodeLine{01496\ \}}
\DoxyCodeLine{01497\ }
\DoxyCodeLine{01505\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableCRC(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01506\ \{}
\DoxyCodeLine{01507\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga25e56eef69334cb723e24a8d33fb0ef5}{SPI\_CFG1\_CRCEN}});}
\DoxyCodeLine{01508\ \}}
\DoxyCodeLine{01509\ }
\DoxyCodeLine{01516\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableCRC(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01517\ \{}
\DoxyCodeLine{01518\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga25e56eef69334cb723e24a8d33fb0ef5}{SPI\_CFG1\_CRCEN}});}
\DoxyCodeLine{01519\ \}}
\DoxyCodeLine{01520\ }
\DoxyCodeLine{01527\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledCRC(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01528\ \{}
\DoxyCodeLine{01529\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga25e56eef69334cb723e24a8d33fb0ef5}{SPI\_CFG1\_CRCEN}})\ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga25e56eef69334cb723e24a8d33fb0ef5}{SPI\_CFG1\_CRCEN}})\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01530\ \}}
\DoxyCodeLine{01531\ }
\DoxyCodeLine{01569\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetCRCWidth(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ CRCLength)}
\DoxyCodeLine{01570\ \{}
\DoxyCodeLine{01571\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae07ebb92fa1d04040cf5f40c38216dbd}{SPI\_CFG1\_CRCSIZE}},\ CRCLength);}
\DoxyCodeLine{01572\ \}}
\DoxyCodeLine{01573\ }
\DoxyCodeLine{01609\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetCRCWidth(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01610\ \{}
\DoxyCodeLine{01611\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae07ebb92fa1d04040cf5f40c38216dbd}{SPI\_CFG1\_CRCSIZE}}));}
\DoxyCodeLine{01612\ \}}
\DoxyCodeLine{01613\ }
\DoxyCodeLine{01627\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetNSSMode(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ NSS)}
\DoxyCodeLine{01628\ \{}
\DoxyCodeLine{01629\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad0e7364142f9a7eb6b5c59897dd8b72d}{SPI\_CFG2\_SSM}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9c9863c4e8e013e090efbe2cc7d82c45}{SPI\_CFG2\_SSOE}},\ NSS);}
\DoxyCodeLine{01630\ \}}
\DoxyCodeLine{01631\ }
\DoxyCodeLine{01642\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetNSSMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01643\ \{}
\DoxyCodeLine{01644\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad0e7364142f9a7eb6b5c59897dd8b72d}{SPI\_CFG2\_SSM}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9c9863c4e8e013e090efbe2cc7d82c45}{SPI\_CFG2\_SSOE}}));}
\DoxyCodeLine{01645\ \}}
\DoxyCodeLine{01646\ }
\DoxyCodeLine{01655\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableNSSPulseMgt(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01656\ \{}
\DoxyCodeLine{01657\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gabe0131b6501f637fa0168c031050818d}{SPI\_CFG2\_SSOM}});}
\DoxyCodeLine{01658\ \}}
\DoxyCodeLine{01659\ }
\DoxyCodeLine{01668\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableNSSPulseMgt(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01669\ \{}
\DoxyCodeLine{01670\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gabe0131b6501f637fa0168c031050818d}{SPI\_CFG2\_SSOM}});}
\DoxyCodeLine{01671\ \}}
\DoxyCodeLine{01672\ }
\DoxyCodeLine{01679\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledNSSPulse(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01680\ \{}
\DoxyCodeLine{01681\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ab40edb77993e6f1343c5999f62e5a157}{CFG2}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gabe0131b6501f637fa0168c031050818d}{SPI\_CFG2\_SSOM}})\ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gabe0131b6501f637fa0168c031050818d}{SPI\_CFG2\_SSOM}})\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01682\ \}}
\DoxyCodeLine{01683\ }
\DoxyCodeLine{01687\ }
\DoxyCodeLine{01691\ }
\DoxyCodeLine{01698\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_RXP(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01699\ \{}
\DoxyCodeLine{01700\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga95289b0733d92829f9f0189574dc1d54}{SPI\_SR\_RXP}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga95289b0733d92829f9f0189574dc1d54}{SPI\_SR\_RXP}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01701\ \}}
\DoxyCodeLine{01702\ }
\DoxyCodeLine{01709\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_TXP(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01710\ \{}
\DoxyCodeLine{01711\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9f7199bbdd797f0238aaaf9cc42e4f64}{SPI\_SR\_TXP}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9f7199bbdd797f0238aaaf9cc42e4f64}{SPI\_SR\_TXP}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01712\ \}}
\DoxyCodeLine{01713\ }
\DoxyCodeLine{01720\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_DXP(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01721\ \{}
\DoxyCodeLine{01722\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga73f785111c63d6e951018ebc0fffacf6}{SPI\_SR\_DXP}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga73f785111c63d6e951018ebc0fffacf6}{SPI\_SR\_DXP}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01723\ \}}
\DoxyCodeLine{01724\ }
\DoxyCodeLine{01731\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_EOT(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01732\ \{}
\DoxyCodeLine{01733\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadf6af11782cace2048e20c18d4d63e1a}{SPI\_SR\_EOT}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadf6af11782cace2048e20c18d4d63e1a}{SPI\_SR\_EOT}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01734\ \}}
\DoxyCodeLine{01735\ }
\DoxyCodeLine{01742\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_TXTF(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01743\ \{}
\DoxyCodeLine{01744\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac0e93a296bc722bab78d526bf1cc2f7d}{SPI\_SR\_TXTF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac0e93a296bc722bab78d526bf1cc2f7d}{SPI\_SR\_TXTF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01745\ \}}
\DoxyCodeLine{01746\ }
\DoxyCodeLine{01753\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_UDR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01754\ \{}
\DoxyCodeLine{01755\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga13d3292e963499c0e9a36869909229e6}{SPI\_SR\_UDR}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga13d3292e963499c0e9a36869909229e6}{SPI\_SR\_UDR}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01756\ \}}
\DoxyCodeLine{01757\ }
\DoxyCodeLine{01764\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_CRCERR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01765\ \{}
\DoxyCodeLine{01766\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4c0cf2db0d5d372242e66e6d7da50b39}{SPI\_SR\_CRCE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga4c0cf2db0d5d372242e66e6d7da50b39}{SPI\_SR\_CRCE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01767\ \}}
\DoxyCodeLine{01768\ }
\DoxyCodeLine{01775\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_MODF(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01776\ \{}
\DoxyCodeLine{01777\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gabaa043349833dc7b8138969c64f63adf}{SPI\_SR\_MODF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gabaa043349833dc7b8138969c64f63adf}{SPI\_SR\_MODF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01778\ \}}
\DoxyCodeLine{01779\ }
\DoxyCodeLine{01786\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_OVR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01787\ \{}
\DoxyCodeLine{01788\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa8d902302c5eb81ce4a57029de281232}{SPI\_SR\_OVR}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa8d902302c5eb81ce4a57029de281232}{SPI\_SR\_OVR}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01789\ \}}
\DoxyCodeLine{01790\ }
\DoxyCodeLine{01797\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_FRE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01798\ \{}
\DoxyCodeLine{01799\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf3e3c940fb46d8b32456c59819e615be}{SPI\_SR\_TIFRE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf3e3c940fb46d8b32456c59819e615be}{SPI\_SR\_TIFRE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01800\ \}}
\DoxyCodeLine{01801\ }
\DoxyCodeLine{01808\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_TSER(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01809\ \{}
\DoxyCodeLine{01810\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5332b248a3daf660df7f13098e75da46}{SPI\_SR\_TSERF}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5332b248a3daf660df7f13098e75da46}{SPI\_SR\_TSERF}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01811\ \}}
\DoxyCodeLine{01812\ }
\DoxyCodeLine{01819\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_SUSP(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01820\ \{}
\DoxyCodeLine{01821\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3294b6597873bd2c0f2acb9e722e18cc}{SPI\_SR\_SUSP}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga3294b6597873bd2c0f2acb9e722e18cc}{SPI\_SR\_SUSP}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01822\ \}}
\DoxyCodeLine{01823\ }
\DoxyCodeLine{01830\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_TXC(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01831\ \{}
\DoxyCodeLine{01832\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1695e2f6e8d042aeae4d9f07e96dfe1a}{SPI\_SR\_TXC}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1695e2f6e8d042aeae4d9f07e96dfe1a}{SPI\_SR\_TXC}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01833\ \}}
\DoxyCodeLine{01834\ }
\DoxyCodeLine{01841\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsActiveFlag\_RXWNE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01842\ \{}
\DoxyCodeLine{01843\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab6334377efffc8f2733962c827a4bf03}{SPI\_SR\_RXWNE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gab6334377efffc8f2733962c827a4bf03}{SPI\_SR\_RXWNE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01844\ \}}
\DoxyCodeLine{01845\ }
\DoxyCodeLine{01852\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetRemainingDataFrames(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01853\ \{}
\DoxyCodeLine{01854\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6f37d39b4458955b93c69ad7c454dfdf}{SPI\_SR\_CTSIZE}})\ >>\ SPI\_SR\_CTSIZE\_Pos);}
\DoxyCodeLine{01855\ \}}
\DoxyCodeLine{01856\ }
\DoxyCodeLine{01867\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetRxFIFOPackingLevel(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01868\ \{}
\DoxyCodeLine{01869\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a33f3dd6a505d06fe6c466b63be451891}{SR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga09c4e3cd9a199757d6f3ac06e5bc110f}{SPI\_SR\_RXPLVL}}));}
\DoxyCodeLine{01870\ \}}
\DoxyCodeLine{01871\ }
\DoxyCodeLine{01878\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_ClearFlag\_EOT(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01879\ \{}
\DoxyCodeLine{01880\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ada4f3c195a523945fca842215c67d8d5}{IFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0a13f7af7ba888d7dbbbf016ccac324b}{SPI\_IFCR\_EOTC}});}
\DoxyCodeLine{01881\ \}}
\DoxyCodeLine{01882\ }
\DoxyCodeLine{01889\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_ClearFlag\_TXTF(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01890\ \{}
\DoxyCodeLine{01891\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ada4f3c195a523945fca842215c67d8d5}{IFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga45f2b0107d9e8789831c616c984088e0}{SPI\_IFCR\_TXTFC}});}
\DoxyCodeLine{01892\ \}}
\DoxyCodeLine{01893\ }
\DoxyCodeLine{01900\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_ClearFlag\_UDR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01901\ \{}
\DoxyCodeLine{01902\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ada4f3c195a523945fca842215c67d8d5}{IFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga13b510c8ba08f0e130469ab6a94c844a}{SPI\_IFCR\_UDRC}});}
\DoxyCodeLine{01903\ \}}
\DoxyCodeLine{01904\ }
\DoxyCodeLine{01911\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_ClearFlag\_OVR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01912\ \{}
\DoxyCodeLine{01913\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ada4f3c195a523945fca842215c67d8d5}{IFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gafe909f94add018dc698a1057b6e174da}{SPI\_IFCR\_OVRC}});}
\DoxyCodeLine{01914\ \}}
\DoxyCodeLine{01915\ }
\DoxyCodeLine{01922\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_ClearFlag\_CRCERR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01923\ \{}
\DoxyCodeLine{01924\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ada4f3c195a523945fca842215c67d8d5}{IFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa776b437fb542da2298b25f64d2b4820}{SPI\_IFCR\_CRCEC}});}
\DoxyCodeLine{01925\ \}}
\DoxyCodeLine{01926\ }
\DoxyCodeLine{01933\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_ClearFlag\_MODF(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01934\ \{}
\DoxyCodeLine{01935\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ada4f3c195a523945fca842215c67d8d5}{IFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga33f5f7e482ff62448df98ed1bef9d62b}{SPI\_IFCR\_MODFC}});}
\DoxyCodeLine{01936\ \}}
\DoxyCodeLine{01937\ }
\DoxyCodeLine{01944\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_ClearFlag\_FRE(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01945\ \{}
\DoxyCodeLine{01946\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ada4f3c195a523945fca842215c67d8d5}{IFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadec3e1c72d5f45f6b9a2681d8275ffb5}{SPI\_IFCR\_TIFREC}});}
\DoxyCodeLine{01947\ \}}
\DoxyCodeLine{01948\ }
\DoxyCodeLine{01955\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_ClearFlag\_TSER(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01956\ \{}
\DoxyCodeLine{01957\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ada4f3c195a523945fca842215c67d8d5}{IFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad058d0a0046d7de998d9d73635009c9e}{SPI\_IFCR\_TSERFC}});}
\DoxyCodeLine{01958\ \}}
\DoxyCodeLine{01959\ }
\DoxyCodeLine{01966\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_ClearFlag\_SUSP(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01967\ \{}
\DoxyCodeLine{01968\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_ada4f3c195a523945fca842215c67d8d5}{IFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga63d88f8a3205e7c27d73e90df3d57a34}{SPI\_IFCR\_SUSPC}});}
\DoxyCodeLine{01969\ \}}
\DoxyCodeLine{01970\ }
\DoxyCodeLine{01974\ }
\DoxyCodeLine{01978\ }
\DoxyCodeLine{01985\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIT\_RXP(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01986\ \{}
\DoxyCodeLine{01987\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga87b292843107573ae82aa13d88916646}{SPI\_IER\_RXPIE}});}
\DoxyCodeLine{01988\ \}}
\DoxyCodeLine{01989\ }
\DoxyCodeLine{01996\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIT\_TXP(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{01997\ \{}
\DoxyCodeLine{01998\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga40ad06dce5bd7f4f2d1db25e8ecd33a4}{SPI\_IER\_TXPIE}});}
\DoxyCodeLine{01999\ \}}
\DoxyCodeLine{02000\ }
\DoxyCodeLine{02007\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIT\_DXP(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02008\ \{}
\DoxyCodeLine{02009\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5fde811db0bae41847c2c56d20e1983b}{SPI\_IER\_DXPIE}});}
\DoxyCodeLine{02010\ \}}
\DoxyCodeLine{02011\ }
\DoxyCodeLine{02018\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIT\_EOT(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02019\ \{}
\DoxyCodeLine{02020\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadd814e85e0f2cc9fd5fbedbd1db232c1}{SPI\_IER\_EOTIE}});}
\DoxyCodeLine{02021\ \}}
\DoxyCodeLine{02022\ }
\DoxyCodeLine{02029\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIT\_TXTF(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02030\ \{}
\DoxyCodeLine{02031\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf329c2e8fb5112c4efdcac4c69bf95fb}{SPI\_IER\_TXTFIE}});}
\DoxyCodeLine{02032\ \}}
\DoxyCodeLine{02033\ }
\DoxyCodeLine{02040\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIT\_UDR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02041\ \{}
\DoxyCodeLine{02042\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga33d0436c4b553cc357b52b9ecaaf542f}{SPI\_IER\_UDRIE}});}
\DoxyCodeLine{02043\ \}}
\DoxyCodeLine{02044\ }
\DoxyCodeLine{02051\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIT\_OVR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02052\ \{}
\DoxyCodeLine{02053\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ba53086c19a3260e0555ace5d700c42}{SPI\_IER\_OVRIE}});}
\DoxyCodeLine{02054\ \}}
\DoxyCodeLine{02055\ }
\DoxyCodeLine{02062\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIT\_CRCERR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02063\ \{}
\DoxyCodeLine{02064\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga298b617fdd0e3d18562509839aa72fa3}{SPI\_IER\_CRCEIE}});}
\DoxyCodeLine{02065\ \}}
\DoxyCodeLine{02066\ }
\DoxyCodeLine{02073\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIT\_FRE(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02074\ \{}
\DoxyCodeLine{02075\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga07f63f1611444f70daf6b08fc18490ee}{SPI\_IER\_TIFREIE}});}
\DoxyCodeLine{02076\ \}}
\DoxyCodeLine{02077\ }
\DoxyCodeLine{02084\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIT\_MODF(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02085\ \{}
\DoxyCodeLine{02086\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6d05af6bd42d7191edec2763928dee98}{SPI\_IER\_MODFIE}});}
\DoxyCodeLine{02087\ \}}
\DoxyCodeLine{02088\ }
\DoxyCodeLine{02095\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableIT\_TSER(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02096\ \{}
\DoxyCodeLine{02097\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1a4844bc9d90e49ba0dcacf7787f2e16}{SPI\_IER\_TSERFIE}});}
\DoxyCodeLine{02098\ \}}
\DoxyCodeLine{02099\ }
\DoxyCodeLine{02106\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableIT\_RXP(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02107\ \{}
\DoxyCodeLine{02108\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga87b292843107573ae82aa13d88916646}{SPI\_IER\_RXPIE}});}
\DoxyCodeLine{02109\ \}}
\DoxyCodeLine{02110\ }
\DoxyCodeLine{02117\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableIT\_TXP(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02118\ \{}
\DoxyCodeLine{02119\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga40ad06dce5bd7f4f2d1db25e8ecd33a4}{SPI\_IER\_TXPIE}});}
\DoxyCodeLine{02120\ \}}
\DoxyCodeLine{02121\ }
\DoxyCodeLine{02128\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableIT\_DXP(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02129\ \{}
\DoxyCodeLine{02130\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5fde811db0bae41847c2c56d20e1983b}{SPI\_IER\_DXPIE}});}
\DoxyCodeLine{02131\ \}}
\DoxyCodeLine{02132\ }
\DoxyCodeLine{02139\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableIT\_EOT(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02140\ \{}
\DoxyCodeLine{02141\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadd814e85e0f2cc9fd5fbedbd1db232c1}{SPI\_IER\_EOTIE}});}
\DoxyCodeLine{02142\ \}}
\DoxyCodeLine{02143\ }
\DoxyCodeLine{02150\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableIT\_TXTF(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02151\ \{}
\DoxyCodeLine{02152\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf329c2e8fb5112c4efdcac4c69bf95fb}{SPI\_IER\_TXTFIE}});}
\DoxyCodeLine{02153\ \}}
\DoxyCodeLine{02154\ }
\DoxyCodeLine{02161\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableIT\_UDR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02162\ \{}
\DoxyCodeLine{02163\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga33d0436c4b553cc357b52b9ecaaf542f}{SPI\_IER\_UDRIE}});}
\DoxyCodeLine{02164\ \}}
\DoxyCodeLine{02165\ }
\DoxyCodeLine{02172\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableIT\_OVR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02173\ \{}
\DoxyCodeLine{02174\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ba53086c19a3260e0555ace5d700c42}{SPI\_IER\_OVRIE}});}
\DoxyCodeLine{02175\ \}}
\DoxyCodeLine{02176\ }
\DoxyCodeLine{02183\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableIT\_CRCERR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02184\ \{}
\DoxyCodeLine{02185\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga298b617fdd0e3d18562509839aa72fa3}{SPI\_IER\_CRCEIE}});}
\DoxyCodeLine{02186\ \}}
\DoxyCodeLine{02187\ }
\DoxyCodeLine{02194\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableIT\_FRE(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02195\ \{}
\DoxyCodeLine{02196\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga07f63f1611444f70daf6b08fc18490ee}{SPI\_IER\_TIFREIE}});}
\DoxyCodeLine{02197\ \}}
\DoxyCodeLine{02198\ }
\DoxyCodeLine{02205\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableIT\_MODF(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02206\ \{}
\DoxyCodeLine{02207\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6d05af6bd42d7191edec2763928dee98}{SPI\_IER\_MODFIE}});}
\DoxyCodeLine{02208\ \}}
\DoxyCodeLine{02209\ }
\DoxyCodeLine{02216\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableIT\_TSER(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02217\ \{}
\DoxyCodeLine{02218\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1a4844bc9d90e49ba0dcacf7787f2e16}{SPI\_IER\_TSERFIE}});}
\DoxyCodeLine{02219\ \}}
\DoxyCodeLine{02220\ }
\DoxyCodeLine{02227\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIT\_RXP(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02228\ \{}
\DoxyCodeLine{02229\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga87b292843107573ae82aa13d88916646}{SPI\_IER\_RXPIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga87b292843107573ae82aa13d88916646}{SPI\_IER\_RXPIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02230\ \}}
\DoxyCodeLine{02231\ }
\DoxyCodeLine{02238\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIT\_TXP(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02239\ \{}
\DoxyCodeLine{02240\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga40ad06dce5bd7f4f2d1db25e8ecd33a4}{SPI\_IER\_TXPIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga40ad06dce5bd7f4f2d1db25e8ecd33a4}{SPI\_IER\_TXPIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02241\ \}}
\DoxyCodeLine{02242\ }
\DoxyCodeLine{02249\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIT\_DXP(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02250\ \{}
\DoxyCodeLine{02251\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5fde811db0bae41847c2c56d20e1983b}{SPI\_IER\_DXPIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5fde811db0bae41847c2c56d20e1983b}{SPI\_IER\_DXPIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02252\ \}}
\DoxyCodeLine{02253\ }
\DoxyCodeLine{02260\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIT\_EOT(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02261\ \{}
\DoxyCodeLine{02262\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadd814e85e0f2cc9fd5fbedbd1db232c1}{SPI\_IER\_EOTIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadd814e85e0f2cc9fd5fbedbd1db232c1}{SPI\_IER\_EOTIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02263\ \}}
\DoxyCodeLine{02264\ }
\DoxyCodeLine{02271\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIT\_TXTF(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02272\ \{}
\DoxyCodeLine{02273\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf329c2e8fb5112c4efdcac4c69bf95fb}{SPI\_IER\_TXTFIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf329c2e8fb5112c4efdcac4c69bf95fb}{SPI\_IER\_TXTFIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02274\ \}}
\DoxyCodeLine{02275\ }
\DoxyCodeLine{02282\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIT\_UDR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02283\ \{}
\DoxyCodeLine{02284\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga33d0436c4b553cc357b52b9ecaaf542f}{SPI\_IER\_UDRIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga33d0436c4b553cc357b52b9ecaaf542f}{SPI\_IER\_UDRIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02285\ \}}
\DoxyCodeLine{02286\ }
\DoxyCodeLine{02293\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIT\_OVR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02294\ \{}
\DoxyCodeLine{02295\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ba53086c19a3260e0555ace5d700c42}{SPI\_IER\_OVRIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ba53086c19a3260e0555ace5d700c42}{SPI\_IER\_OVRIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02296\ \}}
\DoxyCodeLine{02297\ }
\DoxyCodeLine{02304\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIT\_CRCERR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02305\ \{}
\DoxyCodeLine{02306\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga298b617fdd0e3d18562509839aa72fa3}{SPI\_IER\_CRCEIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga298b617fdd0e3d18562509839aa72fa3}{SPI\_IER\_CRCEIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02307\ \}}
\DoxyCodeLine{02308\ }
\DoxyCodeLine{02315\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIT\_FRE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02316\ \{}
\DoxyCodeLine{02317\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga07f63f1611444f70daf6b08fc18490ee}{SPI\_IER\_TIFREIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga07f63f1611444f70daf6b08fc18490ee}{SPI\_IER\_TIFREIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02318\ \}}
\DoxyCodeLine{02319\ }
\DoxyCodeLine{02326\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIT\_MODF(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02327\ \{}
\DoxyCodeLine{02328\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6d05af6bd42d7191edec2763928dee98}{SPI\_IER\_MODFIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6d05af6bd42d7191edec2763928dee98}{SPI\_IER\_MODFIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02329\ \}}
\DoxyCodeLine{02330\ }
\DoxyCodeLine{02337\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledIT\_TSER(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02338\ \{}
\DoxyCodeLine{02339\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_add74ef50f1985dc0afe8af8226d84051}{IER}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1a4844bc9d90e49ba0dcacf7787f2e16}{SPI\_IER\_TSERFIE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1a4844bc9d90e49ba0dcacf7787f2e16}{SPI\_IER\_TSERFIE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02340\ \}}
\DoxyCodeLine{02341\ }
\DoxyCodeLine{02345\ }
\DoxyCodeLine{02349\ }
\DoxyCodeLine{02356\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableDMAReq\_RX(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02357\ \{}
\DoxyCodeLine{02358\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa342a40ac86059d414932474d7ff6edd}{SPI\_CFG1\_RXDMAEN}});}
\DoxyCodeLine{02359\ \}}
\DoxyCodeLine{02360\ }
\DoxyCodeLine{02367\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableDMAReq\_RX(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02368\ \{}
\DoxyCodeLine{02369\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa342a40ac86059d414932474d7ff6edd}{SPI\_CFG1\_RXDMAEN}});}
\DoxyCodeLine{02370\ \}}
\DoxyCodeLine{02371\ }
\DoxyCodeLine{02378\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledDMAReq\_RX(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02379\ \{}
\DoxyCodeLine{02380\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa342a40ac86059d414932474d7ff6edd}{SPI\_CFG1\_RXDMAEN}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa342a40ac86059d414932474d7ff6edd}{SPI\_CFG1\_RXDMAEN}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02381\ \}}
\DoxyCodeLine{02382\ }
\DoxyCodeLine{02389\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_EnableDMAReq\_TX(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02390\ \{}
\DoxyCodeLine{02391\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac2a7b767079c91751283143a40aa0e19}{SPI\_CFG1\_TXDMAEN}});}
\DoxyCodeLine{02392\ \}}
\DoxyCodeLine{02393\ }
\DoxyCodeLine{02400\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_DisableDMAReq\_TX(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02401\ \{}
\DoxyCodeLine{02402\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac2a7b767079c91751283143a40aa0e19}{SPI\_CFG1\_TXDMAEN}});}
\DoxyCodeLine{02403\ \}}
\DoxyCodeLine{02404\ }
\DoxyCodeLine{02411\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_IsEnabledDMAReq\_TX(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02412\ \{}
\DoxyCodeLine{02413\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a1fd1ba3ba655258308d26cdcfaf4bc5e}{CFG1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac2a7b767079c91751283143a40aa0e19}{SPI\_CFG1\_TXDMAEN}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac2a7b767079c91751283143a40aa0e19}{SPI\_CFG1\_TXDMAEN}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02414\ \}}
\DoxyCodeLine{02421\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_DMA\_GetTxRegAddr(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02422\ \{}
\DoxyCodeLine{02423\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)\ \&(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a519806144e513633e6a0093fd554756f}{TXDR}});}
\DoxyCodeLine{02424\ \}}
\DoxyCodeLine{02425\ }
\DoxyCodeLine{02432\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_DMA\_GetRxRegAddr(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02433\ \{}
\DoxyCodeLine{02434\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)\ \&(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a0339afbc47839f09598f7fb09c242b09}{RXDR}});}
\DoxyCodeLine{02435\ \}}
\DoxyCodeLine{02439\ }
\DoxyCodeLine{02443\ }
\DoxyCodeLine{02450\ \_\_STATIC\_INLINE\ uint8\_t\ LL\_SPI\_ReceiveData8(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)\ \textcolor{comment}{/*\ Derogation\ MISRAC2012-\/Rule-\/8.13\ */}}
\DoxyCodeLine{02451\ \{}
\DoxyCodeLine{02452\ \ \ \textcolor{keywordflow}{return}\ (*((\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint8\_t\ *)\&SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a0339afbc47839f09598f7fb09c242b09}{RXDR}}));}
\DoxyCodeLine{02453\ \}}
\DoxyCodeLine{02454\ }
\DoxyCodeLine{02461\ \_\_STATIC\_INLINE\ uint16\_t\ LL\_SPI\_ReceiveData16(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)\ \textcolor{comment}{/*\ Derogation\ MISRAC2012-\/Rule-\/8.13\ */}}
\DoxyCodeLine{02462\ \{}
\DoxyCodeLine{02463\ \textcolor{preprocessor}{\#if\ defined\ (\_\_GNUC\_\_)}}
\DoxyCodeLine{02464\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint16\_t\ *spirxdr\ =\ (\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint16\_t\ *)(\&(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a0339afbc47839f09598f7fb09c242b09}{RXDR}}));}
\DoxyCodeLine{02465\ \ \ \textcolor{keywordflow}{return}\ (*spirxdr);}
\DoxyCodeLine{02466\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02467\ \ \ \textcolor{keywordflow}{return}\ (*((\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint16\_t\ *)\&SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a0339afbc47839f09598f7fb09c242b09}{RXDR}}));}
\DoxyCodeLine{02468\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \_\_GNUC\_\_\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02469\ \}}
\DoxyCodeLine{02470\ }
\DoxyCodeLine{02477\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_ReceiveData32(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)\ \textcolor{comment}{/*\ Derogation\ MISRAC2012-\/Rule-\/8.13\ */}}
\DoxyCodeLine{02478\ \{}
\DoxyCodeLine{02479\ \ \ \textcolor{keywordflow}{return}\ (*((\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)\&SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a0339afbc47839f09598f7fb09c242b09}{RXDR}}));}
\DoxyCodeLine{02480\ \}}
\DoxyCodeLine{02481\ }
\DoxyCodeLine{02489\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_TransmitData8(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint8\_t\ TxData)}
\DoxyCodeLine{02490\ \{}
\DoxyCodeLine{02491\ \ \ *((\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint8\_t\ *)\&SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a519806144e513633e6a0093fd554756f}{TXDR}})\ =\ TxData;}
\DoxyCodeLine{02492\ \}}
\DoxyCodeLine{02493\ }
\DoxyCodeLine{02501\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_TransmitData16(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint16\_t\ TxData)}
\DoxyCodeLine{02502\ \{}
\DoxyCodeLine{02503\ \textcolor{preprocessor}{\#if\ defined\ (\_\_GNUC\_\_)}}
\DoxyCodeLine{02504\ \ \ \mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint16\_t\ *spitxdr\ =\ ((\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint16\_t\ *)\&SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a519806144e513633e6a0093fd554756f}{TXDR}});}
\DoxyCodeLine{02505\ \ \ *spitxdr\ =\ TxData;}
\DoxyCodeLine{02506\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02507\ \ \ *((\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint16\_t\ *)\&SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a519806144e513633e6a0093fd554756f}{TXDR}})\ =\ TxData;}
\DoxyCodeLine{02508\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \_\_GNUC\_\_\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02509\ \}}
\DoxyCodeLine{02510\ }
\DoxyCodeLine{02518\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_TransmitData32(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ TxData)}
\DoxyCodeLine{02519\ \{}
\DoxyCodeLine{02520\ \ \ *((\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\_\_IO}}\ uint32\_t\ *)\&SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a519806144e513633e6a0093fd554756f}{TXDR}})\ =\ TxData;}
\DoxyCodeLine{02521\ \}}
\DoxyCodeLine{02522\ }
\DoxyCodeLine{02530\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetCRCPolynomial(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ CRCPoly)}
\DoxyCodeLine{02531\ \{}
\DoxyCodeLine{02532\ \ \ WRITE\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a03d6f39b695fb8e316e97c8a089cd46b}{CRCPOLY}},\ CRCPoly);}
\DoxyCodeLine{02533\ \}}
\DoxyCodeLine{02534\ }
\DoxyCodeLine{02541\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetCRCPolynomial(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02542\ \{}
\DoxyCodeLine{02543\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a03d6f39b695fb8e316e97c8a089cd46b}{CRCPOLY}}));}
\DoxyCodeLine{02544\ \}}
\DoxyCodeLine{02545\ }
\DoxyCodeLine{02553\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_SPI\_SetUDRPattern(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ Pattern)}
\DoxyCodeLine{02554\ \{}
\DoxyCodeLine{02555\ \ \ WRITE\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a189a6e7526779ec981cd411bc4bd3a51}{UDRDR}},\ Pattern);}
\DoxyCodeLine{02556\ \}}
\DoxyCodeLine{02557\ }
\DoxyCodeLine{02564\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetUDRPattern(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02565\ \{}
\DoxyCodeLine{02566\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a189a6e7526779ec981cd411bc4bd3a51}{UDRDR}}));}
\DoxyCodeLine{02567\ \}}
\DoxyCodeLine{02568\ }
\DoxyCodeLine{02575\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetRxCRC(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02576\ \{}
\DoxyCodeLine{02577\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_aa3d580e3aa375dd3e6c1a3331e819300}{RXCRC}}));}
\DoxyCodeLine{02578\ \}}
\DoxyCodeLine{02579\ }
\DoxyCodeLine{02586\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_SPI\_GetTxCRC(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02587\ \{}
\DoxyCodeLine{02588\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a9fffd568c7ff1da72b24c45c62566abd}{TXCRC}}));}
\DoxyCodeLine{02589\ \}}
\DoxyCodeLine{02590\ }
\DoxyCodeLine{02594\ }
\DoxyCodeLine{02595\ \textcolor{preprocessor}{\#if\ defined(USE\_FULL\_LL\_DRIVER)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02599\ }
\DoxyCodeLine{02600\ ErrorStatus\ LL\_SPI\_DeInit(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx);}
\DoxyCodeLine{02601\ ErrorStatus\ LL\_SPI\_Init(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ LL\_SPI\_InitTypeDef\ *SPI\_InitStruct);}
\DoxyCodeLine{02602\ \textcolor{keywordtype}{void}\ \ \ \ \ \ \ \ LL\_SPI\_StructInit(LL\_SPI\_InitTypeDef\ *SPI\_InitStruct);}
\DoxyCodeLine{02603\ }
\DoxyCodeLine{02607\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ USE\_FULL\_LL\_DRIVER\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{02614\ }
\DoxyCodeLine{02618\ }
\DoxyCodeLine{02619\ \textcolor{comment}{/*\ Private\ variables\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{02620\ \textcolor{comment}{/*\ Private\ constants\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{02621\ \textcolor{comment}{/*\ Private\ macros\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{02622\ }
\DoxyCodeLine{02623\ \textcolor{comment}{/*\ Exported\ types\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{02624\ \textcolor{preprocessor}{\#if\ defined(USE\_FULL\_LL\_DRIVER)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02628\ }
\DoxyCodeLine{02632\ }
\DoxyCodeLine{02633\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{02634\ \{}
\DoxyCodeLine{02635\ \ \ uint32\_t\ Mode;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{02640\ }
\DoxyCodeLine{02641\ \ \ uint32\_t\ Standard;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{02646\ }
\DoxyCodeLine{02647\ }
\DoxyCodeLine{02648\ \ \ uint32\_t\ DataFormat;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{02653\ }
\DoxyCodeLine{02654\ }
\DoxyCodeLine{02655\ \ \ uint32\_t\ MCLKOutput;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{02660\ }
\DoxyCodeLine{02661\ }
\DoxyCodeLine{02662\ \ \ uint32\_t\ AudioFreq;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{02669\ }
\DoxyCodeLine{02670\ }
\DoxyCodeLine{02671\ \ \ uint32\_t\ ClockPolarity;\ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{02676\ }
\DoxyCodeLine{02677\ \}\ LL\_I2S\_InitTypeDef;}
\DoxyCodeLine{02678\ }
\DoxyCodeLine{02682\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*USE\_FULL\_LL\_DRIVER*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{02683\ }
\DoxyCodeLine{02684\ \textcolor{comment}{/*\ Exported\ constants\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{02688\ }
\DoxyCodeLine{02692\ \textcolor{preprocessor}{\#define\ LL\_I2S\_DATAFORMAT\_16B\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{02693\ \textcolor{preprocessor}{\#define\ LL\_I2S\_DATAFORMAT\_16B\_EXTENDED\ \ \ \ \ \ (SPI\_I2SCFGR\_CHLEN)}}
\DoxyCodeLine{02694\ \textcolor{preprocessor}{\#define\ LL\_I2S\_DATAFORMAT\_24B\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_I2SCFGR\_CHLEN\ |\ SPI\_I2SCFGR\_DATLEN\_0)}}
\DoxyCodeLine{02695\ \textcolor{preprocessor}{\#define\ LL\_I2S\_DATAFORMAT\_24B\_LEFT\_ALIGNED\ \ (SPI\_I2SCFGR\_CHLEN\ |\ SPI\_I2SCFGR\_DATLEN\_0\ |\ SPI\_I2SCFGR\_DATFMT)}}
\DoxyCodeLine{02696\ \textcolor{preprocessor}{\#define\ LL\_I2S\_DATAFORMAT\_32B\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_I2SCFGR\_CHLEN\ |\ SPI\_I2SCFGR\_DATLEN\_1)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02700\ }
\DoxyCodeLine{02704\ \textcolor{preprocessor}{\#define\ LL\_I2S\_SLAVE\_VARIABLE\_CH\_LENGTH\ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{02705\ \textcolor{preprocessor}{\#define\ LL\_I2S\_SLAVE\_FIXED\_CH\_LENGTH\ \ \ \ \ \ \ \ (SPI\_I2SCFGR\_FIXCH)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02709\ }
\DoxyCodeLine{02713\ \textcolor{preprocessor}{\#define\ LL\_I2S\_POLARITY\_LOW\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{02714\ \textcolor{preprocessor}{\#define\ LL\_I2S\_POLARITY\_HIGH\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_I2SCFGR\_CKPOL)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02718\ }
\DoxyCodeLine{02722\ \textcolor{preprocessor}{\#define\ LL\_I2S\_STANDARD\_PHILIPS\ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{02723\ \textcolor{preprocessor}{\#define\ LL\_I2S\_STANDARD\_MSB\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_I2SCFGR\_I2SSTD\_0)}}
\DoxyCodeLine{02724\ \textcolor{preprocessor}{\#define\ LL\_I2S\_STANDARD\_LSB\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_I2SCFGR\_I2SSTD\_1)}}
\DoxyCodeLine{02725\ \textcolor{preprocessor}{\#define\ LL\_I2S\_STANDARD\_PCM\_SHORT\ \ \ \ \ \ \ \ \ \ \ (SPI\_I2SCFGR\_I2SSTD\_0\ |\ SPI\_I2SCFGR\_I2SSTD\_1)}}
\DoxyCodeLine{02726\ \textcolor{preprocessor}{\#define\ LL\_I2S\_STANDARD\_PCM\_LONG\ \ \ \ \ \ \ \ \ \ \ \ (SPI\_I2SCFGR\_I2SSTD\_0\ |\ SPI\_I2SCFGR\_I2SSTD\_1\ |\ SPI\_I2SCFGR\_PCMSYNC)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02730\ }
\DoxyCodeLine{02734\ \textcolor{preprocessor}{\#define\ LL\_I2S\_MODE\_SLAVE\_TX\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{02735\ \textcolor{preprocessor}{\#define\ LL\_I2S\_MODE\_SLAVE\_RX\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_I2SCFGR\_I2SCFG\_0)}}
\DoxyCodeLine{02736\ \textcolor{preprocessor}{\#define\ LL\_I2S\_MODE\_SLAVE\_FULL\_DUPLEX\ \ \ \ \ \ \ (SPI\_I2SCFGR\_I2SCFG\_2)}}
\DoxyCodeLine{02737\ \textcolor{preprocessor}{\#define\ LL\_I2S\_MODE\_MASTER\_TX\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_I2SCFGR\_I2SCFG\_1)}}
\DoxyCodeLine{02738\ \textcolor{preprocessor}{\#define\ LL\_I2S\_MODE\_MASTER\_RX\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SPI\_I2SCFGR\_I2SCFG\_1\ |\ SPI\_I2SCFGR\_I2SCFG\_0)}}
\DoxyCodeLine{02739\ \textcolor{preprocessor}{\#define\ LL\_I2S\_MODE\_MASTER\_FULL\_DUPLEX\ \ \ \ \ \ (SPI\_I2SCFGR\_I2SCFG\_2\ |\ SPI\_I2SCFGR\_I2SCFG\_0)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02743\ }
\DoxyCodeLine{02747\ \textcolor{preprocessor}{\#define\ LL\_I2S\_PRESCALER\_PARITY\_EVEN\ \ \ \ \ \ \ \ (0x00000000UL)\ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02748\ \textcolor{preprocessor}{\#define\ LL\_I2S\_PRESCALER\_PARITY\_ODD\ \ \ \ \ \ \ \ \ (0x00000001UL)\ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{02752\ }
\DoxyCodeLine{02756\ \textcolor{preprocessor}{\#define\ LL\_I2S\_FIFO\_TH\_01DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (LL\_SPI\_FIFO\_TH\_01DATA)}}
\DoxyCodeLine{02757\ \textcolor{preprocessor}{\#define\ LL\_I2S\_FIFO\_TH\_02DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (LL\_SPI\_FIFO\_TH\_02DATA)}}
\DoxyCodeLine{02758\ \textcolor{preprocessor}{\#define\ LL\_I2S\_FIFO\_TH\_03DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (LL\_SPI\_FIFO\_TH\_03DATA)}}
\DoxyCodeLine{02759\ \textcolor{preprocessor}{\#define\ LL\_I2S\_FIFO\_TH\_04DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (LL\_SPI\_FIFO\_TH\_04DATA)}}
\DoxyCodeLine{02760\ \textcolor{preprocessor}{\#define\ LL\_I2S\_FIFO\_TH\_05DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (LL\_SPI\_FIFO\_TH\_05DATA)}}
\DoxyCodeLine{02761\ \textcolor{preprocessor}{\#define\ LL\_I2S\_FIFO\_TH\_06DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (LL\_SPI\_FIFO\_TH\_06DATA)}}
\DoxyCodeLine{02762\ \textcolor{preprocessor}{\#define\ LL\_I2S\_FIFO\_TH\_07DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (LL\_SPI\_FIFO\_TH\_07DATA)}}
\DoxyCodeLine{02763\ \textcolor{preprocessor}{\#define\ LL\_I2S\_FIFO\_TH\_08DATA\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (LL\_SPI\_FIFO\_TH\_08DATA)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02767\ }
\DoxyCodeLine{02771\ \textcolor{preprocessor}{\#define\ LL\_I2S\_LSB\_FIRST\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (LL\_SPI\_LSB\_FIRST)}}
\DoxyCodeLine{02772\ \textcolor{preprocessor}{\#define\ LL\_I2S\_MSB\_FIRST\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (LL\_SPI\_MSB\_FIRST)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02776\ }
\DoxyCodeLine{02777\ \textcolor{preprocessor}{\#if\ defined(USE\_FULL\_LL\_DRIVER)}}
\DoxyCodeLine{02778\ }
\DoxyCodeLine{02782\ \textcolor{preprocessor}{\#define\ LL\_I2S\_MCLK\_OUTPUT\_DISABLE\ \ \ \ \ \ \ \ \ \ (0x00000000UL)}}
\DoxyCodeLine{02783\ \textcolor{preprocessor}{\#define\ LL\_I2S\_MCLK\_OUTPUT\_ENABLE\ \ \ \ \ \ \ \ \ \ \ (SPI\_I2SCFGR\_MCKOE)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02787\ }
\DoxyCodeLine{02791\ }
\DoxyCodeLine{02792\ \textcolor{preprocessor}{\#define\ LL\_I2S\_AUDIOFREQ\_192K\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 192000UL\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02793\ \textcolor{preprocessor}{\#define\ LL\_I2S\_AUDIOFREQ\_96K\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 96000UL\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02794\ \textcolor{preprocessor}{\#define\ LL\_I2S\_AUDIOFREQ\_48K\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 48000UL\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02795\ \textcolor{preprocessor}{\#define\ LL\_I2S\_AUDIOFREQ\_44K\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 44100UL\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02796\ \textcolor{preprocessor}{\#define\ LL\_I2S\_AUDIOFREQ\_32K\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 32000UL\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02797\ \textcolor{preprocessor}{\#define\ LL\_I2S\_AUDIOFREQ\_22K\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 22050UL\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02798\ \textcolor{preprocessor}{\#define\ LL\_I2S\_AUDIOFREQ\_16K\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16000UL\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02799\ \textcolor{preprocessor}{\#define\ LL\_I2S\_AUDIOFREQ\_11K\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 11025UL\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02800\ \textcolor{preprocessor}{\#define\ LL\_I2S\_AUDIOFREQ\_8K\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8000UL\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02801\ \textcolor{preprocessor}{\#define\ LL\_I2S\_AUDIOFREQ\_DEFAULT\ \ \ \ \ \ \ \ \ \ \ \ 0UL\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{02805\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ USE\_FULL\_LL\_DRIVER\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02806\ }
\DoxyCodeLine{02810\ }
\DoxyCodeLine{02811\ \textcolor{comment}{/*\ Exported\ macro\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{02815\ }
\DoxyCodeLine{02819\ }
\DoxyCodeLine{02827\ \textcolor{preprocessor}{\#define\ LL\_I2S\_WriteReg(\_\_INSTANCE\_\_,\ \_\_REG\_\_,\ \_\_VALUE\_\_)\ WRITE\_REG(\_\_INSTANCE\_\_-\/>\_\_REG\_\_,\ (\_\_VALUE\_\_))}}
\DoxyCodeLine{02828\ }
\DoxyCodeLine{02835\ \textcolor{preprocessor}{\#define\ LL\_I2S\_ReadReg(\_\_INSTANCE\_\_,\ \_\_REG\_\_)\ READ\_REG(\_\_INSTANCE\_\_-\/>\_\_REG\_\_)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02839\ }
\DoxyCodeLine{02843\ }
\DoxyCodeLine{02844\ }
\DoxyCodeLine{02845\ \textcolor{comment}{/*\ Exported\ functions\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{02846\ }
\DoxyCodeLine{02850\ }
\DoxyCodeLine{02854\ }
\DoxyCodeLine{02869\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_SetDataFormat(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ DataLength)}
\DoxyCodeLine{02870\ \{}
\DoxyCodeLine{02871\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacc12f9d2003ab169a3f68e9d809f84ae}{SPI\_I2SCFGR\_DATLEN}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9c362b3d703698a7891f032f6b29056f}{SPI\_I2SCFGR\_CHLEN}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga22143cbd7b9985dd4a7cf11e7c018d07}{SPI\_I2SCFGR\_DATFMT}},\ DataLength);}
\DoxyCodeLine{02872\ \}}
\DoxyCodeLine{02873\ }
\DoxyCodeLine{02887\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_GetDataFormat(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02888\ \{}
\DoxyCodeLine{02889\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacc12f9d2003ab169a3f68e9d809f84ae}{SPI\_I2SCFGR\_DATLEN}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9c362b3d703698a7891f032f6b29056f}{SPI\_I2SCFGR\_CHLEN}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga22143cbd7b9985dd4a7cf11e7c018d07}{SPI\_I2SCFGR\_DATFMT}}));}
\DoxyCodeLine{02890\ \}}
\DoxyCodeLine{02891\ }
\DoxyCodeLine{02902\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_SetChannelLengthType(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ ChannelLengthType)}
\DoxyCodeLine{02903\ \{}
\DoxyCodeLine{02904\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf6d82e28cd842db16ceb0a36faafbd73}{SPI\_I2SCFGR\_FIXCH}},\ ChannelLengthType);}
\DoxyCodeLine{02905\ \}}
\DoxyCodeLine{02906\ }
\DoxyCodeLine{02916\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_GetChannelLengthType(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02917\ \{}
\DoxyCodeLine{02918\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf6d82e28cd842db16ceb0a36faafbd73}{SPI\_I2SCFGR\_FIXCH}}));}
\DoxyCodeLine{02919\ \}}
\DoxyCodeLine{02920\ }
\DoxyCodeLine{02927\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_EnableWordSelectInversion(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02928\ \{}
\DoxyCodeLine{02929\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac0abe5455caf68d999ee49491f5d196a}{SPI\_I2SCFGR\_WSINV}});}
\DoxyCodeLine{02930\ \}}
\DoxyCodeLine{02931\ }
\DoxyCodeLine{02938\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_DisableWordSelectInversion(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02939\ \{}
\DoxyCodeLine{02940\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac0abe5455caf68d999ee49491f5d196a}{SPI\_I2SCFGR\_WSINV}});}
\DoxyCodeLine{02941\ \}}
\DoxyCodeLine{02942\ }
\DoxyCodeLine{02949\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsEnabledWordSelectInversion(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02950\ \{}
\DoxyCodeLine{02951\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac0abe5455caf68d999ee49491f5d196a}{SPI\_I2SCFGR\_WSINV}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gac0abe5455caf68d999ee49491f5d196a}{SPI\_I2SCFGR\_WSINV}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02952\ \}}
\DoxyCodeLine{02953\ }
\DoxyCodeLine{02963\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_SetClockPolarity(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ ClockPolarity)}
\DoxyCodeLine{02964\ \{}
\DoxyCodeLine{02965\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5c5be1f1c8b4689643e04cd5034e7f5f}{SPI\_I2SCFGR\_CKPOL}},\ ClockPolarity);}
\DoxyCodeLine{02966\ \}}
\DoxyCodeLine{02967\ }
\DoxyCodeLine{02976\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_GetClockPolarity(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{02977\ \{}
\DoxyCodeLine{02978\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5c5be1f1c8b4689643e04cd5034e7f5f}{SPI\_I2SCFGR\_CKPOL}}));}
\DoxyCodeLine{02979\ \}}
\DoxyCodeLine{02980\ }
\DoxyCodeLine{02994\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_SetStandard(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ Standard)}
\DoxyCodeLine{02995\ \{}
\DoxyCodeLine{02996\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7a822a80be3a51524b42491248f8031f}{SPI\_I2SCFGR\_I2SSTD}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga66a29efc32a31f903e89b7ddcd20857b}{SPI\_I2SCFGR\_PCMSYNC}},\ Standard);}
\DoxyCodeLine{02997\ \}}
\DoxyCodeLine{02998\ }
\DoxyCodeLine{03011\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_GetStandard(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03012\ \{}
\DoxyCodeLine{03013\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7a822a80be3a51524b42491248f8031f}{SPI\_I2SCFGR\_I2SSTD}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga66a29efc32a31f903e89b7ddcd20857b}{SPI\_I2SCFGR\_PCMSYNC}}));}
\DoxyCodeLine{03014\ \}}
\DoxyCodeLine{03015\ }
\DoxyCodeLine{03029\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_SetTransferMode(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ Standard)}
\DoxyCodeLine{03030\ \{}
\DoxyCodeLine{03031\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf09fd11f6f97000266b30b015bf2cb68}{SPI\_I2SCFGR\_I2SCFG}},\ Standard);}
\DoxyCodeLine{03032\ \}}
\DoxyCodeLine{03033\ }
\DoxyCodeLine{03046\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_GetTransferMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03047\ \{}
\DoxyCodeLine{03048\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf09fd11f6f97000266b30b015bf2cb68}{SPI\_I2SCFGR\_I2SCFG}}));}
\DoxyCodeLine{03049\ \}}
\DoxyCodeLine{03050\ }
\DoxyCodeLine{03058\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_Enable(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03059\ \{}
\DoxyCodeLine{03060\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae99763414b3c2f11fcfecb1f93eb6701}{SPI\_I2SCFGR\_I2SMOD}});}
\DoxyCodeLine{03061\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac5a646d978d3b98eb7c6a5d95d75c3f9}{SPI\_CR1\_SPE}});}
\DoxyCodeLine{03062\ \}}
\DoxyCodeLine{03063\ }
\DoxyCodeLine{03071\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_Disable(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03072\ \{}
\DoxyCodeLine{03073\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a6ecd5cb63b85c381bd67dc90dd4f573a}{CR1}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gac5a646d978d3b98eb7c6a5d95d75c3f9}{SPI\_CR1\_SPE}});}
\DoxyCodeLine{03074\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae99763414b3c2f11fcfecb1f93eb6701}{SPI\_I2SCFGR\_I2SMOD}});}
\DoxyCodeLine{03075\ \}}
\DoxyCodeLine{03076\ }
\DoxyCodeLine{03084\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_EnableIOSwap(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03085\ \{}
\DoxyCodeLine{03086\ \ \ LL\_SPI\_EnableIOSwap(SPIx);}
\DoxyCodeLine{03087\ \}}
\DoxyCodeLine{03088\ }
\DoxyCodeLine{03096\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_DisableIOSwap(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03097\ \{}
\DoxyCodeLine{03098\ \ \ LL\_SPI\_DisableIOSwap(SPIx);}
\DoxyCodeLine{03099\ \}}
\DoxyCodeLine{03100\ }
\DoxyCodeLine{03107\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsEnabledIOSwap(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03108\ \{}
\DoxyCodeLine{03109\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsEnabledIOSwap(SPIx);}
\DoxyCodeLine{03110\ \}}
\DoxyCodeLine{03111\ }
\DoxyCodeLine{03119\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_EnableGPIOControl(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03120\ \{}
\DoxyCodeLine{03121\ \ \ LL\_SPI\_EnableGPIOControl(SPIx);}
\DoxyCodeLine{03122\ \}}
\DoxyCodeLine{03123\ }
\DoxyCodeLine{03131\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_DisableGPIOControl(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03132\ \{}
\DoxyCodeLine{03133\ \ \ LL\_SPI\_DisableGPIOControl(SPIx);}
\DoxyCodeLine{03134\ \}}
\DoxyCodeLine{03135\ }
\DoxyCodeLine{03142\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsEnabledGPIOControl(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03143\ \{}
\DoxyCodeLine{03144\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsEnabledGPIOControl(SPIx);}
\DoxyCodeLine{03145\ \}}
\DoxyCodeLine{03146\ }
\DoxyCodeLine{03155\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_EnableIOLock(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03156\ \{}
\DoxyCodeLine{03157\ \ \ LL\_SPI\_EnableIOLock(SPIx);}
\DoxyCodeLine{03158\ \}}
\DoxyCodeLine{03159\ }
\DoxyCodeLine{03166\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsEnabledIOLock(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03167\ \{}
\DoxyCodeLine{03168\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsEnabledIOLock(SPIx);}
\DoxyCodeLine{03169\ \}}
\DoxyCodeLine{03170\ }
\DoxyCodeLine{03181\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_SetTransferBitOrder(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ BitOrder)}
\DoxyCodeLine{03182\ \{}
\DoxyCodeLine{03183\ \ \ LL\_SPI\_SetTransferBitOrder(SPIx,\ BitOrder);}
\DoxyCodeLine{03184\ \}}
\DoxyCodeLine{03193\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_GetTransferBitOrder(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03194\ \{}
\DoxyCodeLine{03195\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_GetTransferBitOrder(SPIx);}
\DoxyCodeLine{03196\ \}}
\DoxyCodeLine{03197\ }
\DoxyCodeLine{03204\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_StartTransfer(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03205\ \{}
\DoxyCodeLine{03206\ \ \ LL\_SPI\_StartMasterTransfer(SPIx);}
\DoxyCodeLine{03207\ \}}
\DoxyCodeLine{03208\ }
\DoxyCodeLine{03215\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsActiveTransfer(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03216\ \{}
\DoxyCodeLine{03217\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsActiveMasterTransfer(SPIx);}
\DoxyCodeLine{03218\ \}}
\DoxyCodeLine{03219\ }
\DoxyCodeLine{03236\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_SetFIFOThreshold(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ Threshold)}
\DoxyCodeLine{03237\ \{}
\DoxyCodeLine{03238\ \ \ LL\_SPI\_SetFIFOThreshold(SPIx,\ Threshold);}
\DoxyCodeLine{03239\ \}}
\DoxyCodeLine{03240\ }
\DoxyCodeLine{03255\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_GetFIFOThreshold(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03256\ \{}
\DoxyCodeLine{03257\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_GetFIFOThreshold(SPIx);}
\DoxyCodeLine{03258\ \}}
\DoxyCodeLine{03259\ }
\DoxyCodeLine{03268\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_SetPrescalerLinear(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ PrescalerLinear)}
\DoxyCodeLine{03269\ \{}
\DoxyCodeLine{03270\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2b1a83146bd901493a172ba549345da2}{SPI\_I2SCFGR\_I2SDIV}},\ (PrescalerLinear\ <<\ SPI\_I2SCFGR\_I2SDIV\_Pos));}
\DoxyCodeLine{03271\ \}}
\DoxyCodeLine{03272\ }
\DoxyCodeLine{03279\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_GetPrescalerLinear(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03280\ \{}
\DoxyCodeLine{03281\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2b1a83146bd901493a172ba549345da2}{SPI\_I2SCFGR\_I2SDIV}})\ >>\ SPI\_I2SCFGR\_I2SDIV\_Pos);}
\DoxyCodeLine{03282\ \}}
\DoxyCodeLine{03283\ }
\DoxyCodeLine{03293\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_SetPrescalerParity(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ PrescalerParity)}
\DoxyCodeLine{03294\ \{}
\DoxyCodeLine{03295\ \ \ MODIFY\_REG(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga34081019e9fa193f6ce3c0f3d34d8852}{SPI\_I2SCFGR\_ODD}},\ PrescalerParity\ <<\ SPI\_I2SCFGR\_ODD\_Pos);}
\DoxyCodeLine{03296\ \}}
\DoxyCodeLine{03297\ }
\DoxyCodeLine{03306\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_GetPrescalerParity(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03307\ \{}
\DoxyCodeLine{03308\ \ \ \textcolor{keywordflow}{return}\ (uint32\_t)(READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga34081019e9fa193f6ce3c0f3d34d8852}{SPI\_I2SCFGR\_ODD}})\ >>\ SPI\_I2SCFGR\_ODD\_Pos);}
\DoxyCodeLine{03309\ \}}
\DoxyCodeLine{03310\ }
\DoxyCodeLine{03317\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_EnableMasterClock(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03318\ \{}
\DoxyCodeLine{03319\ \ \ SET\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacc14a03f240b4f9ea4f8885f21df80f2}{SPI\_I2SCFGR\_MCKOE}});}
\DoxyCodeLine{03320\ \}}
\DoxyCodeLine{03321\ }
\DoxyCodeLine{03328\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_DisableMasterClock(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03329\ \{}
\DoxyCodeLine{03330\ \ \ CLEAR\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacc14a03f240b4f9ea4f8885f21df80f2}{SPI\_I2SCFGR\_MCKOE}});}
\DoxyCodeLine{03331\ \}}
\DoxyCodeLine{03332\ }
\DoxyCodeLine{03339\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsEnabledMasterClock(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03340\ \{}
\DoxyCodeLine{03341\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(SPIx-\/>\mbox{\hyperlink{struct_s_p_i___type_def_a4a1547c0ed26f31108910c35d2876b83}{I2SCFGR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacc14a03f240b4f9ea4f8885f21df80f2}{SPI\_I2SCFGR\_MCKOE}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gacc14a03f240b4f9ea4f8885f21df80f2}{SPI\_I2SCFGR\_MCKOE}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{03342\ \}}
\DoxyCodeLine{03343\ }
\DoxyCodeLine{03347\ }
\DoxyCodeLine{03348\ }
\DoxyCodeLine{03352\ }
\DoxyCodeLine{03359\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsActiveFlag\_RXP(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03360\ \{}
\DoxyCodeLine{03361\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsActiveFlag\_RXP(SPIx);}
\DoxyCodeLine{03362\ \}}
\DoxyCodeLine{03363\ }
\DoxyCodeLine{03370\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsActiveFlag\_TXP(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03371\ \{}
\DoxyCodeLine{03372\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsActiveFlag\_TXP(SPIx);}
\DoxyCodeLine{03373\ \}}
\DoxyCodeLine{03374\ }
\DoxyCodeLine{03381\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsActiveFlag\_UDR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03382\ \{}
\DoxyCodeLine{03383\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsActiveFlag\_UDR(SPIx);}
\DoxyCodeLine{03384\ \}}
\DoxyCodeLine{03385\ }
\DoxyCodeLine{03392\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsActiveFlag\_OVR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03393\ \{}
\DoxyCodeLine{03394\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsActiveFlag\_OVR(SPIx);}
\DoxyCodeLine{03395\ \}}
\DoxyCodeLine{03396\ }
\DoxyCodeLine{03403\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsActiveFlag\_FRE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03404\ \{}
\DoxyCodeLine{03405\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsActiveFlag\_FRE(SPIx);}
\DoxyCodeLine{03406\ \}}
\DoxyCodeLine{03407\ }
\DoxyCodeLine{03414\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_ClearFlag\_UDR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03415\ \{}
\DoxyCodeLine{03416\ \ \ LL\_SPI\_ClearFlag\_UDR(SPIx);}
\DoxyCodeLine{03417\ \}}
\DoxyCodeLine{03418\ }
\DoxyCodeLine{03425\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_ClearFlag\_OVR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03426\ \{}
\DoxyCodeLine{03427\ \ \ LL\_SPI\_ClearFlag\_OVR(SPIx);}
\DoxyCodeLine{03428\ \}}
\DoxyCodeLine{03429\ }
\DoxyCodeLine{03436\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_ClearFlag\_FRE(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03437\ \{}
\DoxyCodeLine{03438\ \ \ LL\_SPI\_ClearFlag\_FRE(SPIx);}
\DoxyCodeLine{03439\ \}}
\DoxyCodeLine{03440\ }
\DoxyCodeLine{03444\ }
\DoxyCodeLine{03448\ }
\DoxyCodeLine{03455\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_EnableIT\_RXP(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03456\ \{}
\DoxyCodeLine{03457\ \ \ LL\_SPI\_EnableIT\_RXP(SPIx);}
\DoxyCodeLine{03458\ \}}
\DoxyCodeLine{03459\ }
\DoxyCodeLine{03466\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_EnableIT\_TXP(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03467\ \{}
\DoxyCodeLine{03468\ \ \ LL\_SPI\_EnableIT\_TXP(SPIx);}
\DoxyCodeLine{03469\ \}}
\DoxyCodeLine{03470\ }
\DoxyCodeLine{03477\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_EnableIT\_UDR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03478\ \{}
\DoxyCodeLine{03479\ \ \ LL\_SPI\_EnableIT\_UDR(SPIx);}
\DoxyCodeLine{03480\ \}}
\DoxyCodeLine{03481\ }
\DoxyCodeLine{03488\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_EnableIT\_OVR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03489\ \{}
\DoxyCodeLine{03490\ \ \ LL\_SPI\_EnableIT\_OVR(SPIx);}
\DoxyCodeLine{03491\ \}}
\DoxyCodeLine{03492\ }
\DoxyCodeLine{03499\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_EnableIT\_FRE(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03500\ \{}
\DoxyCodeLine{03501\ \ \ LL\_SPI\_EnableIT\_FRE(SPIx);}
\DoxyCodeLine{03502\ \}}
\DoxyCodeLine{03503\ }
\DoxyCodeLine{03510\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_DisableIT\_RXP(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03511\ \{}
\DoxyCodeLine{03512\ \ \ LL\_SPI\_DisableIT\_RXP(SPIx);}
\DoxyCodeLine{03513\ \}}
\DoxyCodeLine{03514\ }
\DoxyCodeLine{03521\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_DisableIT\_TXP(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03522\ \{}
\DoxyCodeLine{03523\ \ \ LL\_SPI\_DisableIT\_TXP(SPIx);}
\DoxyCodeLine{03524\ \}}
\DoxyCodeLine{03525\ }
\DoxyCodeLine{03532\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_DisableIT\_UDR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03533\ \{}
\DoxyCodeLine{03534\ \ \ LL\_SPI\_DisableIT\_UDR(SPIx);}
\DoxyCodeLine{03535\ \}}
\DoxyCodeLine{03536\ }
\DoxyCodeLine{03543\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_DisableIT\_OVR(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03544\ \{}
\DoxyCodeLine{03545\ \ \ LL\_SPI\_DisableIT\_OVR(SPIx);}
\DoxyCodeLine{03546\ \}}
\DoxyCodeLine{03547\ }
\DoxyCodeLine{03554\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_DisableIT\_FRE(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03555\ \{}
\DoxyCodeLine{03556\ \ \ LL\_SPI\_DisableIT\_FRE(SPIx);}
\DoxyCodeLine{03557\ \}}
\DoxyCodeLine{03558\ }
\DoxyCodeLine{03565\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsEnabledIT\_RXP(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03566\ \{}
\DoxyCodeLine{03567\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsEnabledIT\_RXP(SPIx);}
\DoxyCodeLine{03568\ \}}
\DoxyCodeLine{03569\ }
\DoxyCodeLine{03576\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsEnabledIT\_TXP(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03577\ \{}
\DoxyCodeLine{03578\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsEnabledIT\_TXP(SPIx);}
\DoxyCodeLine{03579\ \}}
\DoxyCodeLine{03580\ }
\DoxyCodeLine{03587\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsEnabledIT\_UDR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03588\ \{}
\DoxyCodeLine{03589\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsEnabledIT\_UDR(SPIx);}
\DoxyCodeLine{03590\ \}}
\DoxyCodeLine{03591\ }
\DoxyCodeLine{03598\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsEnabledIT\_OVR(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03599\ \{}
\DoxyCodeLine{03600\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsEnabledIT\_OVR(SPIx);}
\DoxyCodeLine{03601\ \}}
\DoxyCodeLine{03602\ }
\DoxyCodeLine{03609\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsEnabledIT\_FRE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03610\ \{}
\DoxyCodeLine{03611\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsEnabledIT\_FRE(SPIx);}
\DoxyCodeLine{03612\ \}}
\DoxyCodeLine{03613\ }
\DoxyCodeLine{03617\ }
\DoxyCodeLine{03621\ }
\DoxyCodeLine{03628\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_EnableDMAReq\_RX(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03629\ \{}
\DoxyCodeLine{03630\ \ \ LL\_SPI\_EnableDMAReq\_RX(SPIx);}
\DoxyCodeLine{03631\ \}}
\DoxyCodeLine{03632\ }
\DoxyCodeLine{03639\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_DisableDMAReq\_RX(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03640\ \{}
\DoxyCodeLine{03641\ \ \ LL\_SPI\_DisableDMAReq\_RX(SPIx);}
\DoxyCodeLine{03642\ \}}
\DoxyCodeLine{03643\ }
\DoxyCodeLine{03650\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsEnabledDMAReq\_RX(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03651\ \{}
\DoxyCodeLine{03652\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsEnabledDMAReq\_RX(SPIx);}
\DoxyCodeLine{03653\ \}}
\DoxyCodeLine{03654\ }
\DoxyCodeLine{03661\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_EnableDMAReq\_TX(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03662\ \{}
\DoxyCodeLine{03663\ \ \ LL\_SPI\_EnableDMAReq\_TX(SPIx);}
\DoxyCodeLine{03664\ \}}
\DoxyCodeLine{03665\ }
\DoxyCodeLine{03672\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_DisableDMAReq\_TX(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03673\ \{}
\DoxyCodeLine{03674\ \ \ LL\_SPI\_DisableDMAReq\_TX(SPIx);}
\DoxyCodeLine{03675\ \}}
\DoxyCodeLine{03676\ }
\DoxyCodeLine{03683\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_IsEnabledDMAReq\_TX(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)}
\DoxyCodeLine{03684\ \{}
\DoxyCodeLine{03685\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_IsEnabledDMAReq\_TX(SPIx);}
\DoxyCodeLine{03686\ \}}
\DoxyCodeLine{03687\ }
\DoxyCodeLine{03691\ }
\DoxyCodeLine{03695\ }
\DoxyCodeLine{03702\ \_\_STATIC\_INLINE\ uint16\_t\ LL\_I2S\_ReceiveData16(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)\ \textcolor{comment}{/*\ Derogation\ MISRAC2012-\/Rule-\/8.13\ */}}
\DoxyCodeLine{03703\ \{}
\DoxyCodeLine{03704\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_ReceiveData16(SPIx);}
\DoxyCodeLine{03705\ \}}
\DoxyCodeLine{03706\ }
\DoxyCodeLine{03713\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_I2S\_ReceiveData32(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx)\ \textcolor{comment}{/*\ Derogation\ MISRAC2012-\/Rule-\/8.13\ */}}
\DoxyCodeLine{03714\ \{}
\DoxyCodeLine{03715\ \ \ \textcolor{keywordflow}{return}\ LL\_SPI\_ReceiveData32(SPIx);}
\DoxyCodeLine{03716\ \}}
\DoxyCodeLine{03717\ }
\DoxyCodeLine{03725\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_TransmitData16(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint16\_t\ TxData)}
\DoxyCodeLine{03726\ \{}
\DoxyCodeLine{03727\ \ \ LL\_SPI\_TransmitData16(SPIx,\ TxData);}
\DoxyCodeLine{03728\ \}}
\DoxyCodeLine{03729\ }
\DoxyCodeLine{03737\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_I2S\_TransmitData32(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ TxData)}
\DoxyCodeLine{03738\ \{}
\DoxyCodeLine{03739\ \ \ LL\_SPI\_TransmitData32(SPIx,\ TxData);}
\DoxyCodeLine{03740\ \}}
\DoxyCodeLine{03741\ }
\DoxyCodeLine{03742\ }
\DoxyCodeLine{03746\ }
\DoxyCodeLine{03747\ }
\DoxyCodeLine{03748\ \textcolor{preprocessor}{\#if\ defined(USE\_FULL\_LL\_DRIVER)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03752\ }
\DoxyCodeLine{03753\ ErrorStatus\ LL\_I2S\_DeInit(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx);}
\DoxyCodeLine{03754\ ErrorStatus\ LL\_I2S\_Init(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ \textcolor{keyword}{const}\ LL\_I2S\_InitTypeDef\ *I2S\_InitStruct);}
\DoxyCodeLine{03755\ \textcolor{keywordtype}{void}\ \ \ \ \ \ \ \ LL\_I2S\_StructInit(LL\_I2S\_InitTypeDef\ *I2S\_InitStruct);}
\DoxyCodeLine{03756\ \textcolor{keywordtype}{void}\ \ \ \ \ \ \ \ LL\_I2S\_ConfigPrescaler(\mbox{\hyperlink{struct_s_p_i___type_def}{SPI\_TypeDef}}\ *SPIx,\ uint32\_t\ PrescalerLinear,\ uint32\_t\ PrescalerParity);}
\DoxyCodeLine{03757\ }
\DoxyCodeLine{03761\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ USE\_FULL\_LL\_DRIVER\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03762\ }
\DoxyCodeLine{03766\ }
\DoxyCodeLine{03770\ }
\DoxyCodeLine{03771\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined(SPI1)\ ||\ defined(SPI2)\ ||\ defined(SPI3)\ ||\ defined(SPI4)\ ||\ defined(SPI5)\ ||\ defined(SPI6)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03772\ }
\DoxyCodeLine{03776\ }
\DoxyCodeLine{03777\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{03778\ \}}
\DoxyCodeLine{03779\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{03780\ }
\DoxyCodeLine{03781\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32H7xx\_LL\_SPI\_H\ */}\textcolor{preprocessor}{}}

\end{DoxyCode}
